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DATE: 05-28-2016 HOTFIX VERSION: 071
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CCRID PRODUCT PRODUCTLEVEL2 TITLE. Q, m8 T. c8 } ~6 Q
===================================================================================================================================
" \* A7 a. K, U" [; F1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets5 ^) o5 k6 [. a9 ]: b6 @
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
4 i3 s( H6 q7 y( f7 N1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
9 b) J3 P* Z; @: z1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
5 u D. X% \) ]1 O- L1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.8 I3 s0 b! s( _, I V
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
# A5 d+ d& K/ a- Z1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
# I# b) G; y( T" F3 t1 A1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
& `7 }+ x, n: J1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
/ O, S& Q; v! z7 V! i [$ Y1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library W: d8 O/ a) @! r/ W
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
9 w2 ?9 m) j" X1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon; {; o* ~2 G9 A: p) G, c9 C/ T
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
" v8 h! a$ {3 j% z& w5 l1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open" V9 R* P9 h" p; r5 n: ? h
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters( ]* `: o' @' g5 x3 v/ P5 z
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC4 o9 }: u7 Y& c3 U
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins, u, k: L( Z' @+ d6 V& w) c
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas e8 d+ R5 T; D, M! _
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
7 q' g3 T$ K$ O7 E- ?/ v1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
5 B8 z/ N$ h/ |5 p9 C1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.* Y5 A1 @' m& y
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct9 i5 {3 Y: O6 ~
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window- w* x& w# k( e
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'" p$ U7 Y( z* P6 T
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
1 P6 n) G# q6 a/ P1 L3 z: L" q1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...6 W: }# z1 R2 O1 P
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
! j, I {7 n. Y9 z" M6 t1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short+ m9 b, h2 Z& F9 j( z5 Z X- `8 Q8 u# h
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property- d/ k/ T G0 w- T* i; _6 r+ b! L8 X
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
* e' }- [' \/ z2 x& x. j& N9 O1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display2 m% S( g! X; K1 B7 g% i1 X& W
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
6 p9 a1 N6 x( z# M6 S1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file, ?8 [. n: i+ @+ H! ?4 a
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings& `& r% {) }. b- n& s' B
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
% ] m @$ K8 W. V" p7 i1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
6 g" @; d3 X; u" V! e0 L1 K/ ` r, O* f K0 T/ \
DATE: 04-22-2016 HOTFIX VERSION: 069
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
) s+ i9 H6 \% x2 U _% {0 \1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode, X3 Z& r/ \0 e- N) S
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail: e. B v) j: ^# e* x
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol1 C- O" ^# c/ h1 e/ U
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing6 ]5 a7 O! P* P/ y" X$ N, I
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
' n' c4 q) u' g! r% F- s1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
" Z; e8 ]5 l) Z8 j& v1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
% f8 u( L! q/ s/ n: I# P7 e1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
+ p6 U. P, K& M8 @' b1 H; o1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder; }& m% t9 h P7 p
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
, t2 e% h: D/ M% {1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork4 F4 d8 i+ f1 G3 e2 |
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message: f: r1 C* y3 c9 f6 E# _
1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point- E) \ e( b( {
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
$ Q5 e9 f3 ~! ^: o |1 v8 O' W1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems/ `5 X+ V+ O( m5 `) D. `3 X0 t. Y
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro# p/ w5 E& s3 Q5 M
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups5 w/ K7 T4 u% H
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
0 \# X0 b7 T: u; r1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
6 k% r7 m; k2 _" b" _1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted, ]3 u& u; t3 C1 \2 k: ]+ [
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
+ z; b; g6 Z# _1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM+ C4 Z7 n- J( {3 ^) w* ^( Z+ H) {5 }6 v
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error
. e6 q5 }: A: \6 F5 z* m7 N( `1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.# X# `% H" m6 F0 z% P: U9 k) l
# N: t) J- y( o2 C% p# Z. Y' G, e0 VDATE: 03-23-2016 HOTFIX VERSION: 068& x4 Y( H+ i4 h! c2 U
===================================================================================================================================2 R7 H0 j! x& | T$ D+ h9 r
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 O' _' p y/ _* |/ g3 L
===================================================================================================================================
3 A" b9 ~7 H! ?1 L. h: r! r3 V5 C2 p1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
@, M3 \: ^; \! \* r2 m1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file( {) J. k }- j' p7 g0 X
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license, s" t5 p2 h! i8 }3 Q# X/ G
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short' Y) z& m- y, g. Y. ^" y
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system. d: U; D1 J4 @" v
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected./ _( a* _* L' c% V x2 n& ~& f2 I
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol( x3 ]$ k5 W/ \! v8 W& e( c
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file& c! O- J8 r5 B( [' C/ q( e c
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report/ ? n6 z# M+ t' A( P4 d! T4 W( c
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
6 f6 _- `: S, x- x0 N1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .; j0 H+ s/ b* i. z6 L7 ~
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts1 m6 L! h( Q B
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols! f* _$ b P5 C# ?! y j) X
0 J* n) j* x# O2 }3 B! O
DATE: 03-11-2016 HOTFIX VERSION: 067
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===================================================================================================================================
# D; B4 o" D& a7 a1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
$ }# o T! R) |' }9 j9 H1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
) _* V5 H+ }9 d4 S1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error% {, @4 `- b/ [8 `, F1 U7 ^9 i
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'/ e# k: L7 \" g
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property5 U$ v: D( j. U* p. i
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
% m" \6 t2 ]0 h* c! ?1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file* n" _& r' O# c7 n' E4 u. f& U
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
, b# k+ r3 a# \5 U7 Z1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing& k* B; ]$ `: f
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager; m5 E2 {4 ?4 w7 `, e" K$ x* Z
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters1 P$ m9 I$ ^' @# ~0 e8 M
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
$ @+ c7 o% {" a1 Z6 B7 c, ?1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer5 G* E G5 ~4 ~6 C
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
- U3 d0 d2 s R2 Q; {$ _* {( R1 ^1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
2 C5 d1 G8 J; i% ^" c1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
; @$ u: d7 k& O$ ~. i1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
1 F" I+ `' j+ _2 p1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.
* c L+ _! r1 Z2 V1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib/ W9 ~1 d4 j, z7 i6 p
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines
* ~, E/ H J6 K" ~1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
4 j. v% z0 F( H$ H! l& x( @0 Q4 @1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
/ k4 L, C2 s8 [% Q4 O1 @8 _# Z3 Q% Y1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash, C6 Q) F2 K* |
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
3 p( p! F/ \# o1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
9 ^/ y! }: Y8 K0 w- M6 C1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
$ L* F; x$ [' }$ @3 a" z: }! y }1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with$ J% `+ c9 Z, {' \( m
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design+ l% P& U) c/ l' Y$ x. e
3 ]- J* F7 P$ H9 p7 zDATE: 02-26-2016 HOTFIX VERSION: 066) B4 f ^! {0 c3 S* ~8 [" L) J
===================================================================================================================================+ C' \1 o# v( }6 u2 t2 o. u4 [
CCRID PRODUCT PRODUCTLEVEL2 TITLE
- ?8 T7 M, `$ \& a===================================================================================================================================
6 h' e# T, w6 V: v1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
1 u5 \; [3 T4 d( W1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
* d& v5 L8 t' K! h9 ~) ]( H ~1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions T9 z$ D# y) U! w; K f: o
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
2 l" [( x& A# ]# t1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr u* V( {. V% n. H7 k
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
. h0 j I) v/ `2 s0 m3 k* k1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer! _4 {; |7 M4 z: @$ M6 `+ {
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
) E# d) P7 @" q5 R9 v g+ C1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run
: r) A9 i; }# C7 L1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed5 d& m' e. J: M# [+ \3 s& {. g
0 U, ?5 j3 @0 d% UDATE: 02-12-2016 HOTFIX VERSION: 065
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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( n' y' Y9 D R! A' F* L# o1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
# h7 ]+ C! n7 @9 ?1 `1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
0 X2 t, b& q8 L9 e% J' E1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit( L& d2 R5 C9 a8 s! [- H: `6 J
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
7 I3 Z9 ~6 z. ]1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms( S' J% M, n+ X: H
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine, o; }5 R. H3 l. }. w4 c7 V
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger
1 r+ D# L$ l* V5 I9 y( J1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design6 f. @8 } n& m
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
7 u2 c( [, P4 [- N1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.+ a+ m" O8 o! e+ O0 t, G
, A" n! Q7 ~4 E) N" |1 r6 xDATE: 01-29-2016 HOTFIX VERSION: 064% l4 E) V" w0 C' s3 F% k
===================================================================================================================================
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1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain4 H3 w! d3 d2 f- ]1 ]" D+ T
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF9 Q9 G3 ~1 J, W2 M. Z
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties. M0 k! Y" }- }4 c# C* m
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected( [2 x7 @7 Z& ^- Z/ \. P: C# y' q! ]
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.+ m% F1 r) l$ X- d
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
* H( }% X o* \1 C8 m" o" A1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas
8 I+ e1 F" D/ B {1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net5 m3 G4 x9 g8 U/ q
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
1 k2 t H" y$ X M; B# k1 l1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic$ I& P8 y+ ]+ `2 J
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
7 Q4 ?3 x& q/ w9 v8 T1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)4 s/ K$ r; q4 A( v! ]
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design( ^, I+ u4 j f5 l
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
4 b; m0 s1 d: E( y4 J7 b1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes f) N3 _& R6 ]( `1 B! |6 j# i
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
- I7 j" ?5 z, H- Y+ L' ^: s. G1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
( u0 [& }1 s2 G9 Q1 B0 Q9 @: V% p5 e1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
! w( B, |/ O/ ~1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
7 ^9 m2 m+ } a1 p3 C! r `
' p) w2 W# Y+ v7 [DATE: 01-15-2016 HOTFIX VERSION: 063
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9 w' T; \* C" v: D4 Z' sCCRID PRODUCT PRODUCTLEVEL2 TITLE
" d% f, Z0 F9 S===================================================================================================================================
2 K/ o* o7 y' e Y1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
& u+ ?4 C# e5 p7 _3 ?1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs+ a c* U) J% Z8 X3 r$ s
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs, i2 Z9 }6 W Y, k
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant9 D1 h: q) g6 l
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork3 Q9 P2 n/ u! u3 B
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6+ y+ n3 |" k. Z; d5 h- n
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
) M& a8 W H: V& ~+ ~; Q$ m, Q1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.% G: I5 _5 _3 e6 [
1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.
( L6 C: B. T9 t; k$ C; f1 A1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out# q5 [- ? p- T4 t0 \0 N
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
& j% ~& T( G7 ? F. J, V6 G% E1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
+ I1 Y6 s6 }, g- f1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
4 ?( V7 [" v& j9 Y6 p. [1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation/ `7 |6 f7 \+ j' {$ e/ |& J
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol9 m( W1 w9 G" D" Y `' Y* }
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
4 e. o5 q- _ C0 q' I$ Z! U/ d1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
, q$ v( A! k C- P' A" A# S1519518 CONCEPT_HDL OTHER Genview does not generate split symbols: X' Q2 B4 n) [
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas2 j1 B3 g! d+ U% X" s) r9 ?
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports( `; j1 T$ W3 L# P% s! E
& Z" H7 U# `( q! W2 A
DATE: 12-11-2015 HOTFIX VERSION: 062
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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) y! ^' o& l) V- _4 y1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
( U8 ?: k% h, y* Z+ N6 L+ Z1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
! L# ^5 r3 r4 \5 y8 Z1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
4 u: V! l0 o% [; A8 S1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC2 B* Y) h1 X$ G
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view7 b% F2 I* Y/ `7 Y) B
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked1 `2 i/ p1 q2 u4 {+ y
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.6 Q+ C% F6 J. W# z6 U# b
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file# }8 z1 l- J( d5 R
1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding1 p) {3 n( V) G& q' {! S! g
1490311 SCM OTHER Block Packaging reports duplication when it should not
: ^) Y6 ?2 G# S. p" L* ?& q* R h: G6 y1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
7 U) P! i8 z7 r$ a5 c2 d1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
) z @' [$ Z. Q1 g9 N8 @' y, o1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
# T# i+ U# \' c6 V# h& ~1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
# ^5 v4 H; A3 c# n! o1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
' Q1 O* n. \ _1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )6 X# n2 I8 J9 Y' R& x
1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
7 ]# _$ Q$ `6 ^ W% [- P4 q, a1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'! L( _1 u* ]/ G' i/ w: S" B. c3 m
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly0 N3 e U6 N& ]5 n
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this0 f# R& `) L; W* ?" x* r" {
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
+ L+ g/ o/ T3 t* m0 f1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
6 Y, ~3 A f# t, _% U1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
# u0 K7 K0 F2 I1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
; f- B9 V5 ]. d" H1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out/ Y8 R9 i: A5 v" \/ z3 C0 g; P) Y. l
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
/ ^2 L! D% H7 X& O, f. A, [+ d1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
% q" u. w) j& h( P; T$ ?4 u& A1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL2 |$ j! V, j: y4 C5 i& Y2 u: B$ {" @ Y7 x
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings) {3 h- q9 o3 ^/ b3 I
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
2 l6 n9 C1 L i1 m, i1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
* T5 L8 n' W* c8 L4 w1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary# e3 v2 p" z' g- f6 q" w6 Q3 a
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items' g2 d: N" B D& r! f
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin6 N0 G" s1 g$ X
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving1 `# N: F- Q2 |' x a1 B
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None% k* y+ h% \0 k3 W% E* M
0 R ]' J0 u; l0 eDATE: 11-20-2015 HOTFIX VERSION: 061
+ j9 Y0 ^! `. p& C1 W$ ]===================================================================================================================================
: D2 B) {: m9 kCCRID PRODUCT PRODUCTLEVEL2 TITLE4 ?& K% D/ Z+ h3 o/ {$ U5 l
===================================================================================================================================
& m. ?& ^ @- b1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
1 i [# ]. Z+ x. s6 c3 G+ _) T1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
7 E5 O3 q8 B9 V1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
# w, C- P; s9 \1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle# s$ j4 b6 F6 f1 { k' w" ~ h! T( g
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
. F5 Z K1 _: k, p( a% X/ A: O1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set1 i) k7 Y" }9 ]* t
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
$ Q2 K, ]" c2 d! L9 Y( G' y1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
* }/ H) o& R2 H" [! @* N |# z1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename" c1 t. k6 m# t
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
5 e9 [( K/ \* {7 b1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL! C0 i! @; y4 H, M9 H" {3 ?
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy' Y. E+ h, n# Q9 I
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable* S0 B; m2 F; s
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
9 \/ Z1 x8 w0 G9 i+ l- ^9 k1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
4 [# J2 S, Z B5 _# O8 A1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
% c, ] y' w7 p7 i1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only: a% N* Y8 Q& ~
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
& \5 Q7 i( a1 w7 q) N. v1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
7 `7 ~) H) x3 z& }) P1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility! v. {. c& t& t8 U
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems. M9 F$ y8 ^9 a& S7 G" j1 a* c# ~
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported' v8 Q& \3 r/ \' H% b- ]
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior! y1 |! ]0 |; K
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
: C& I1 \, U7 V! i2 u& h. E2 N1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager) a, n5 H) X/ u# d& d
1490299 SCM OTHER ASA does not update revision properly4 A) Q) g0 ]4 d0 y/ H# q
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer# _+ v' f. l: M7 @
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
* ?2 ^( g+ x# u5 E: [" s" k$ A1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
& L- @( U: y- A. Z! \9 k S+ z% t( j1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong# x: @( t# P/ h3 ]) D
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
8 p1 M8 \# p8 y* a1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
4 X. }) o# d: F- h- A" P: x6 T8 i1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581+ }4 R9 `9 h! F' D" I8 I" ?
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
& L4 V' v' [7 Y+ F" `& {1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
( b# g8 a/ P" S# `' r8 ~1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file# u: \+ t- K5 G
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05
