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4 @9 a" L3 S& Q& i4 a- Y 才看到网友说AD15出来了，然后刷微博就看到了这个。。。
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1 h7 ~ C* b+ z" [- f& l" S! ] s' D ~9 M# n* g* o5 X
AltiumDesigner15.0.7出来了！
0 A' u1 i, H% J: V9 D我唯一的感觉就是，Altium，你更新的太快了啊！有事没事，你就更新，- w# o9 }( t, Y1 _7 h" a
或者说是，你是在修Bug么？？
& o1 x2 b( g- W& ]貌似AD14就一直是Bug不断，这次AD15估计也一样，不过，0 [$ b% I! v4 U7 W9 X
貌似AD15更新了高速PCB设计和GerberX2的支持。具体更新如下。
/ e0 p: { [7 y' }2 ?0 J就一个问题，AD总是在不停的更新，是表示软件不稳定呢，还是？？？
$ }. c, I2 W! h4 W# p; ^' ?; B或者说，你会更新到AltiumDesigner15版本么？9 M0 R3 {0 E+ E& R! L* v: g! Y" a% @( Z
8 ~; A- X) \' i/ y6 T& ZRelease Notes for Altium Designer Version 15.00 B, ]3 [% d6 T( o0 b/ D
Modified by Nikolay Ponomarenko on 17-Nov-2014
) ^, C3 i7 T+ u3 b) ]3 B8 _9 nKey feature highlights: C, e' X' U* `9 z! y
High Speed Design with xSignals
( h# J1 ]4 D. D1 F" `. j5 pSolder Mask Expansion Enhancements
9 d" e% I! W! O7 x+ I4 ]" jAccurate Route Length Calculation: l- T% V& `7 E2 K" {
Polygon Enhancements1 i- D9 c& w. f+ w# i) z! K7 F' h. P
OLE Object Support in PCB Documents$ C1 Q6 q. B N. e, g
Support for Rectangular Pad Holes) @1 d2 s$ A5 }1 h6 W, w
Separate 2D & 3D View Orientations. `$ A _' a+ I% h6 V3 o0 @3 R6 D
IPC-2581 Support b+ e$ {, `; J; L/ O6 e- {& R; g
Gerber X2 Support' c" C# h% A H
IDX Support. h0 O" }- y' F" {$ F5 L0 x) W
Exporting to IDF in Unicode Format
( H8 b9 r7 }: H, K, K8 ^( zTrue Variants Enhancements: m! I1 X" @9 c( g1 p
Output Job Editor Enhancements
0 \$ B3 n g4 S) n FUpgraded Duplicate UID Correction8 t6 O/ H y9 I! a5 `" I
System and Performance Enhancements6 D% ?% P1 o" C7 m* H
Vault Connection Enhancements$ h% ` M/ D& e- a
Ability to Control Parameter Visibility for Vault Components
9 b5 ?( c2 m8 g) `) ]" H) x$ vParameter List Templates+ {7 e& o& ?/ H
Parameter-based Name Templates
: L( W: K* k8 l" h' mVivado toolchain improvements
& M. k {6 h7 L* S, N. FIntuitive Import and Export
* L1 v4 L, @) E: ?0 UVersion 15.0.7
H3 T4 H: \% b" dBuild: 36915 Date:17 November 2014
h; T6 h" T+ x) [0 ^2 o, r1015 Support for high DPI screens using oversized fonts has been reviewed and improved.* Y& Y$ X4 x( ]# Y0 h9 J
1335 PCB NC drill layer pair reports now correctly report layer spans for blind/buried via holes,/ f* T }0 Y9 j( ~$ w! y
when layers are shuffled out of default order.8 C. C5 F% u& f! k
1381 Export to AutoCAD now correctly includes thru-hole pad geometries and holes./ N9 D3 F. m- q
1382 After certain editing sequences the PCB editor would incorrectly switch to masking the display,2 o5 d' b7 ~. ^0 q K
this no longer occurs. g7 s& D& r% O: h1 N
1408 IDF export now includes an option to export in Unicode format.% ~9 U) v4 B6 Y- }
1615 Changing PCB layer names could result in layer-related lists populating incorrectly and certain
+ ? J" b; F$ V. k2 v* D! Noutputs not generating correctly, this has been fixed.
1 B- Y& S4 \% N( h2613 A Vault Content Cart can now target regular folders.
! {- P* A& V* c( Q" m/ B2816 It is now possible to define a CmpLib Component Naming scheme using a template with
, V" ^# ^ u ?& }! zvalues from any parameter, for example CMP-[Value]-[PackageReference]-{0001}.. d" w# q5 J2 B0 O0 ]7 p
2817% I; J( ~" E' K
The CmpLib editor now supports the addition of new parameters via customizable parameter$ c1 H8 V9 t) ~' y1 z# I3 h4 H
list templates. Click the Required Models/Parameters Add button to access the templates' C! `! ~. I# t! y5 H
(samples are stored in the \Templates folder).; q) v: u- ?) N8 r. E4 E0 h
2855 Duplicate UniqueIDs are detected by the Schematic compiler and detailed in the Messages8 M& P" b, I2 b0 `- q; x$ A
panel. Existing duplicate UIDs are also automatically resolved during document loading.9 t; p' V4 F" v" O, q! J9 w
2910 Release Notes column is now available when using Vault-based libraries in the Libraries panel.
3 \/ J5 X. K8 M7 r5 F0 P" A) r3006 The Component Cuts Wire mode now functions correctly when the Always Drag option is
6 q) D* Y! M$ v8 Menabled.! ^! n) e" k6 U7 d# V
30089 v) L4 Z) f* }/ H
OutputJob Editor enhanced by the addition of: mouse wheel scrolling & scroll bars when not/ m7 V# R# E( F4 y
all Jobs/Containers are visible, drag and drop to change Job order, multi-Job Enable/Disable
% l' |6 \3 @. ^* G. N8 r/ |right-click commands & shortcuts (select the container first).
* u: Q8 g8 c. y5 ?3026 Import and Export options are now directly accessible via the Files menu. Save As commands
3 l, s& Z! L! \# D# U2 C* I9 @! iare now used exclusively for Altium file formats. (BC:1812, BC:2731 partial)
: S- l' a. H) T8 H9 F; b; {$ a7 M3033 Gerber X2 is now available as an output format. It supports output generation via the PCB
* K( A5 n0 b, J1 ?5 feditor Fabrication Outputs menu, or via an OutputJob. \) n% X3 `" P
3035
/ c% d, q9 l' D+ W0 RIPC-2581B is now available as an output format. Install the extension and generate output via
* B. {9 H, b0 cthe PCB editor Fabrication Outputs menu, or via an OutputJob. Download a free viewer from; a, B0 ~. ^ |6 J. I- N
http://www.ipc2581.com/index.php/ipc-2581-files
+ `* n: s$ f8 S% I9 L3081 The Vaults panel now supports changing the column visibility and order. These changes,
& U0 @/ N8 u- y; c$ Z* F( u7 xalong with panel-section resize actions are retained between sessions./ a+ G6 F) n2 Y! i) f6 \( f& k0 h
3143 Timeout errors after releasing project documents to a Vault have been fixed.
9 B- S* f3 @ J- Q6 ?, G9 l3188 OutputJobs now support using a slash character in the Output Container Name.
' } a' g+ h7 j, q; ]( `3189/ b ~! |9 Q8 M; u4 g0 N, A
It is now possible to pre-configure the display state of Vault component parameters, via the
6 s; h! x( q. l" s7 c( EVault Folder Properties dialog (Type = altium-component-library) and the Vault Library dialog7 v& R5 @! w8 f, w N
(add a Vault as a Library).* a3 \' u( _2 E6 G' u
3205 Switching from the logical to the physical tab of a schematic no longer leaves artifacts on the
% w% S) r- v- n# n: A2 s; Oscreen.
" `' A+ i1 B* D1 s( Z3225 Schematic dragging has been further developed to improve wire/bus bending and reduce the
, M/ j% L: b6 e) m6 ~! a2 Y1 R. }* {likelihood of a netlist change., n" d/ @" {( c$ r( y* q
3227 Schematic dragging has been further developed to improve object handling and the quality of& ^7 j+ _6 h1 b) z6 q6 C
the result, and reduce the likelihood of a netlist change.' e3 I3 ~/ u- h+ Q3 y+ I
3232 Polygon vertex deletion using Ctrl+Hover+Click is now working correctly. Hold the left mouse
- d8 L$ x' @4 q. E Tbutton down as you click, until the vertex disappears.6 z5 I m; v! P9 C/ h5 B) G
3251 Releasing projects to the vault with file-locking being enabled works correctly now H1 g: Z+ Z% G7 z& j3 A3 H
3272 The schematic library editor panel now supports standard copy and paste shortcuts, Ctrl+C
* d, v2 q& R: l: M( Aand Ctrl+V.) b- R! c3 f$ J* w d n% o: n( f
3293 BOM filters no longer mix up the parameters. Note that for an existing BOM the filters must be! m& F+ a% _0 P" D4 i$ H
cleared, the BOM saved, closed and re-opened, and the filters re-defined.! C% T! w8 x5 |& a: U
3338 Multi-net routing no longer creates a clearance violation at corners when the Converge5 n* F9 n8 S4 D; ], V# y1 U" S
shortcut (C) is pressed.; l- }; N3 {! V6 s
3341 When a PDF is generated from a schematic that includes a hyperlink, clicking the hyperlink
" `2 [/ ?" e: i$ k+ L. S- lnow opens the target web page correctly.
% `' k6 T5 x5 j$ O! h3357 Teardrop removal speed has been improved.8 D* P0 L2 }& S- H8 Q
3381 Second click to select an individual segment in a schematic wire now works correctly.7 s3 L: m V4 [" K
3412 The issue with not being able to close documents having "=" character in their name has
9 @! s! Q2 b2 S) k( Dbeen resolved9 m" J* t2 C; ^3 j6 E( s
3419 When the Interactive Router is in push mode, a via on the pushing net can push other-net
' T c0 I/ P& X" E. O8 p) _objects, including vias.
" ]" J7 S1 \+ _3423 A specific Verilog HDL project would cause an AV on compile, this no longer occurs.! j+ Z8 Z! _% ]2 S/ K% I# e" x
3425 Update from Libraries now correctly preserves existing location and orientation of parameter
! [! s8 t- n9 f" d2 p' mstrings.
. Q: P4 u/ b# z @. z+ m8 e3437 2D and 3D PCB view orientations are now completely separate, each retains the previous
# r3 j; e9 R4 m( z( Gorientation and zoom when switching between the views.' R9 f4 }8 W3 C' f. G
3441
9 u* r) y$ A4 D7 uPin-pairs have been added to the PCB editor, delivering the ability to define the path and
) [! @# G9 C. @: l8 hconstraints for a signal to travel between a source and destination, through termination
, s+ n, H6 X2 ~components and y-splits.% W# v+ q5 A' q0 r I0 U1 @
3442 The import of complex arc shapes from AutoCAD has been improved.
. E/ F& A3 ?/ R' }8 }: Y j3 w3443 The PCB Editor now supports embedding OLE objects, such as Word or Excel documents, into; ?' d2 h+ H5 E I) T
a PCB document (Place В» Object from File).- M( k! T9 I$ X' Z1 [- T% H Q5 E! v
3456 Xilinx Vivado toolchain is now correctly detected, and can also be added manually in the FPGA" H9 B$ i, O2 d' Z) i [' a* b U
- Place and Route preference settings.
- b+ P- r; a/ J \3457 Split plane editing could occasionally cause an exception, this no longer occurs.) {; A; K* u+ c6 n R
3459: Y& Y- ]( t3 ~# \+ q+ E$ _; Q* H& H
When a wire is placed perpendicular to multiple schematic pins and then dragged, a wire
# T' v( \/ j" O4 D0 Ysegment is automatically added between every pin and the wire being dragged. This fix8 g& r, H- k/ F! S/ }- T3 ~
restores previous schematic editing behavior.# u) d$ L3 T. b
3477 Schematic library editor, the Parameter Manager now supports editing parameters across( T0 S! r, K! m5 Y' d% A {3 P# S
multiple selected components.
- }( e9 n, j" B3492 A warning is displayed when you attempt to complete an invalid blanket (has intersecting1 R" q- s, U) S8 G+ Y
edges) in the schematic editor.5 q G: E7 E i9 l4 E& ?
3495 PCB component fanout now functions correctly when there is an unpoured polygon under the
* s! X! e3 C2 h& V% G2 G- Gcomponent.$ Q; \$ L6 Q7 {
3497 Click and drag to move a group of selected objects now be functions correctly.
s* i& U$ L! ~: j6 }4 Y+ z3498 An exception that occurred during import of specific DxDesigner projects has been resolved.
5 u: S2 p3 x& H3514 PCB Step model import has been enhanced with better support for curved shapes.
0 L4 \5 r$ o% {3521 Fileless editing of an external SIM model no longer generates an AV.3 b) n" t: n5 F/ A2 x
3528 AVS 1.1 is now supported by Altium Designer 14.3.+ j% l3 z3 n# R9 A" C
3529 Component pads placed on a signal layer other than top or bottom could not be edited in. H9 o' z) ]3 Z1 e9 t, b( T
certain layer-stack configurations, this no longer occurs.
0 j% T3 c2 C2 b$ Q3530 Top and Bottom Solder Mask layers are now included in the PCB Filter panel's Layer list.
* X$ t5 t1 h* H3 h1 l* \( q9 }3546 The IPC Footprint Wizard now previews 2-pin and 3-pin DFN component correctly.4 @/ v1 V6 a2 f9 J' r
3551 Schematic auto-junctions now size correctly regardless of the wire width.! A. ^9 U% f5 `' m0 D+ A' {, K% X, h
3556 Component primitives placed on mechanical layer 17 or higher now have their layer displayed
- c' X) l7 Z9 |' Z; [/ Hcorrectly in the Components mode of the PCB Panel.9 M; E, |2 [5 y- b
3560 It is now possible to connect to an SVN repository with a user name containing the @3 M( Q3 [0 q- o0 z9 {
character.$ ~" _" x$ A, e+ G0 ]
3561 The correct Lifecycle and Naming Schema is now being loaded during CmpLib file-less editing.
, Z1 J' A6 L3 Z" ~$ J3567 Model selection drop-downs in the CmpLib editor now display the Lifecycle state in color.
/ I- | M6 s7 O) V8 Z. k2 w3568 The Vaults panel now shows the Note data from the correct Lifecycle state.
; M( U0 T% Y2 B' E3576 PDF generated by running OutputJob can be opened directly from OutputJob document: X8 o. x9 Q7 c# B" h P( \; u8 l
3577 Simulation model pin mapping now works correctly in the CmpLib editor.
$ {! ?) ?, C: I1 b+ m j/ j( t3585 Pin swapping was not correctly generating an ECO after performing PCB pin swapping, this
3 g. w, s4 N& ^5 s* u% Y$ T& z0 ahas been resolved.
3 j2 k0 U* S) ~( s7 s1 h7 C* V; H3592 The path tracing routines used for creating a polygon from selected primitives have been- n c; L: u# \9 p' ]/ o+ |5 x
improved, to better handle small objects and multiple paths.
9 X# ]" c' k: n3 `5 S( R3598 From-To panel now shows length taking via heights into account
+ O$ v% Z- @ L4 u# H: ]3611 The schematic Place Wire command now correctly retains the corner mode used in the
9 X( J* B$ X; b. O8 Fprevious wire placement.% c" h& q1 l+ h) F8 ?9 ~
3626 Vault-defined part choice currencies are now used in Altium Designer supplier dialogues
; ^1 ^ h+ ^% a* h- Y& ^3633 Updating Altium Designer from an NIS no longer requires a current Portal connection.
4 u* m3 e& |8 K' f) k; M0 F3634 "Access denied" error when installing an update from NIS has been resolved
# x- z2 \& P- P" h" h3640 Support for rectangular-shaped pad holes has been added. `5 |7 T+ y) ^' Y) c1 a
3664 PCB exception while re-building a net to an arc center point in a specific design no longer0 A I1 P; u. \1 K
occurs.$ [* E! ?, b4 g4 ~) v6 \" s! @
3681 Plane connects (thermal reliefs) are now shown correctly when board is flipped5 t6 P4 w1 [5 F$ f! D- x
3689 Exception no longer occurs when choosing PCB font style in VariantManager (BC:4664)+ o# f" {! n; N" s
3692 Pads with rotated square holes no longer show copper still being present after running the$ X+ \6 n+ l/ d
Remove Unused Pad Shape command./ r; Q9 e. ~% ]7 b, K: L
3695 GOST specific documents can now be generated in BOM Report outputs
, Q! z" M$ J5 i( e( b3707 "No model link found for component" error no longer occurs while editing old cmplib files
1 K; x. Q' `8 P3708 Clicking on a supplier part number in the Vaults panel no longer causes an exception.; s, }% `8 Q; m
3721 Occasional exceptions during a print preview no longer occur.# P4 G) ?0 ~" p6 ~
3722 Under certain conditions changes made in the Variant Management dialog could cause an
6 Q, A# b) s" m2 }/ F6 g% L$ B U3 pexception, this no longer occurs.1 i; ], I! E1 M5 W- ^
3729 The Variant Management dialog now immediately reflects changes to components, such as
# V3 b. V4 q$ |# ]- X% _( xclearing or choosing an Alternate Part, improving usability.0 ]4 y# Y9 I3 f) ~
3732 The Edit action is now available when right-clicking in the Search results panel in the4 x/ z- [6 T# }) I5 g* q8 ?2 s
VaultExplorer: y* O9 r4 c+ [+ L# C( a$ J, G
3736 Fixed error while releasing Vault revisions with extra long file and path names" ?, P* _ I7 B; z: ^2 x/ f
3737 Changes to Comment and Description are no longer lost during component release from the
% s: Q* }$ W, _CmpLib editor, y# n; n; c0 B
3739 A Length column has been added to the Primitives table in the Nets view of the PCB panel
& p% P2 Y' A& w b. [3755 Scope section of the Teardrops dialog was modified to distinguish TH and SMD pads
& x3 T. D- V% J7 i) I3757 Duplicate Port UIDs no longer cause Port names to be changed when generating a PDF from3 I! j# n2 E* f# ?6 z
the schematic.5 k0 x. ~7 `' i. W5 @1 x* r
3774 Under certain conditions, schematic compile masks did not exclude components or net1 A4 c# u/ i: R% a% F0 C- r
objects underneath them, this has been resolved.
1 W; }/ H# S# V ^9 B" M3778 On a schematic with a lot of wiring, placing a wire with the Break Wires at Autojunction option
/ S8 G. Q+ m5 K! lenabled was very slow, this has been optimized.# L8 I K- R: ?
3779 Improved performance of selection and zooming in Schematic in comparison with 14.3, M [; j! k: s1 C0 _& h
3785 Under certain conditions it was possible to get the PCB Layer Stack Manager graphical
5 D- E" ]- c L+ b6 Q) Rrepresentation out of sync with the tabular layer detail region, this has been resolved. L, H- M' p F2 d- m* ]
3787 The " rint as a single job" option in Output Job File documents now properly combines the
9 l0 Q0 _8 ?$ X( D/ m0 z$ P9 Jseparate documents to a single print output/ I d; B- r+ o& x0 N( V$ H6 O- f
3789( l8 Y3 [" T* h
PCB re-annotation on a variant design with not-fitted parts could result in the varied parts% |+ x0 R$ B, N0 H: m
becoming out of sync, this no longer occurs. Note: PCB re-annotation on a design that uses: K H7 i% B* I. [! m! P$ W2 |
alternate parts with different footprints is not yet supported./ D* Q; ~, N5 n0 J- h+ o5 y
3792 STEP models from Inventor 2014 are now loaded without errors4 P P- y; t8 f. J! y
3800 Variant PCB drawing options have been updated to make it easier to understand how Not; _0 Q1 R5 u7 m/ u( t- [
Fitted components are displayed.
( m5 M2 ]- t, }4 `0 v, g3809 It is now possible to specify different values for solder mask expansions for top and bottom
* c3 n: c( L- R2 t% |layers) D( a5 t; f" O4 Y* E4 l5 _
3834 Empty surface constructs are now suppressed in ODB++ fabrication output.& Q' I1 l) j% k7 U$ V3 G+ k* }
3835 The IPC footprint wizard now correctly supports defining PLCC packages with different D and E
0 o& t) H j- Hpin counts, allowing packages with any even number of pins to be created.- O y( \( H. g0 M* }
3836 Dragging multiple schematic wire ends could occasionally result in one wire being shorter
2 o, J9 ~# D, `" ~than the rest, this no longer occurs.2 X8 Z5 R9 P$ C) m- q! y) b/ V
3841 Reset All command added to the Variant Manager, use this to restore all parameters to
; A0 J4 Q' w+ W- ^7 \8 \, I" walternate or base component values.
o6 \# ?1 h# z v3844 The issue resulting in "I/O error 103" error message when some of the project files are
6 v: N9 h9 T6 sread-only has been resolved/ ^3 r, ]3 M; \' N$ N" O" g2 S
3845 The speed of updating from libraries or a database has been improved for designs that
9 K% M# H" d! O8 S Z& Z% \2 Winclude variants using alternate parts.+ O; \ a5 ?- }' O7 I, g
3849 In certain circumstances a component would still be shown as varied after resetting; M/ s ~" O$ I# X. k# g
parameter variations, this has been resolved.7 [4 e6 g5 X' _: K' _
3857 Polygon management was improved in comparison with 14.3 (restored shelving, modified8 v# ~+ s8 T6 l
concept). e) n- Q( B0 m X/ U
3875 The Vaults panel right-click menus now display correctly when Display scaling is being used.
; X" t( `, H& n3 }! k3876 Elements of the Vaults panel were being compressed when Display scaling is being used, this
" R- J! j* d; C4 v/ {$ Mno longer occurs." h; o6 O* U8 h0 j
3888 Crash reports can now be send from behind a proxy
9 A( Q9 r2 E, ~2 z8 \4 s0 a3889 Simulation Waveform viewer print preview issue has been fixed.3 y2 r; m' Q w1 S1 k" W
3900 Class generation settings are now stored for device sheets (BC:3840); ]5 |" O* q7 {8 [* t
3903 The time to open the PCB Classes dialog has been substantially reduced, particularly on3 ]% z" Q) z" g4 m# B! S/ U
designs with a large number of classes.3 [0 A2 n; }1 H1 U8 W+ m% \+ N
3972 ODB++ output did not generate drill data for drill holes included in a panel, when none of the2 [5 x, ?/ m, ?: P, |( f
embedded boards had drill holes, this has been resolved.& d' \9 _2 V* E- _9 n) K* P0 W* Y3 g
3984 Drawing of Schematic Blanket directives has been further optimized to get them to draw
" j3 \6 k# F* N* @quickly and also correctly display the fill color.- Q3 K, ~( b# @$ ` e
4005 Variant designs that include alternate parts with different footprints can now be re-annotated
4 @7 M9 r8 m% G9 ]in the PCB editor.
& s! h/ @; v; Z7 q5 U4016 PCB DRC now supports stacked alternate parts in a variant-based design.$ A3 \7 X) C6 f& m+ H) B/ x
4049 Signal length column was added to Nets panel (this length is being calculated using more
3 i# T! M4 I3 v7 q7 _precise xSignal engine)
3 y- A5 r- k6 R9 y4062 All extensions within a group can now be installed in a single action.
9 q# F, o& ~0 _: f- S1 ~4069 Some PCB dialogs were ignoring the board units and always displaying in mils, this no longer
' _' l" U7 F/ n8 t, q" joccurs.) A9 E; ~7 m. F B' |
4076 Modified Polygon rule support check for shelved polygons" N5 i% L/ T2 Z" u5 X4 b% d
4083 During import of a P-CAD PCB file the layer types are now correctly detected and assigned for
7 R- ^3 `; h# r2 P! c9 aall possible layer configurations.
+ F1 g$ W% T4 N( ?' ~" B, s4092 The DRC Violations Display page of the Preferences dialog now displays the complete list of
+ f6 A+ h+ T" @' _6 W1 qDisplay Style entries when Windows display scaling is being used.6 f8 j- g$ [: o& d! r* L5 [5 l
4098 An AV could occur while placing a pin in a schematic library and pressing Esc to quit the
6 p3 z; w# M8 C: Y5 I" D4 rcommand, this no longer happens.% K) ^' a5 N/ D A% G2 G8 r
4111 With a specific combination of preferences, placing a component from the schematic libraries. S! O8 K6 B$ y) p. x, {+ k, `
panel could cause Altium Designer to crash, this no longer occurs.2 M( D" g) D* W
4121 After configuring components for pin swapping, it is no longer necessary for the designer to( w- K* G4 v2 [5 Z
manually recompile the design to make those swap configurations available.
: I7 w+ L: \5 O4 m. W: H# e* C+ k& n4133 Changes made in the FPGA Signal Manager are now correctly added to the constraint file.* k$ S; a( n. J \, j
4135 Silk to Solder Mask design rule now correctly detects both silk to solder mask or silk to copper2 @9 G2 |7 a. K2 c6 {
rule check configurations.
9 s3 W9 z$ O, e% s4215 When a polygon is shelved, connections created by the polygon are maintained internally so
' q6 s3 p b: Ethe connection lines will not be displayed.* ^6 Q: V' j2 S" t3 \! g/ i3 ?
4351 NIOS II CPU does not generates with Altera Quartus version 13.0 or later2 [' I1 g) J6 D- u/ |1 x3 v, A+ G
Source URL: http://techdocs.altium.com/display/ADOH/Release+Notes+for+Altium+Designer+Version+15.0
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发表于 2014-11-21 18:54
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