|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
DATE: 07-31-2015 HOTFIX VERSION: 054
3 S' @! v1 l3 x: s8 j/ C" g7 H===================================================================================================================================
$ d4 y y* r6 I! j7 DCCRID PRODUCT PRODUCTLEVEL2 TITLE1 K7 B7 U8 P+ L) U
===================================================================================================================================0 a1 _* r1 m! L& B6 t
694479 CONCEPT_HDL OTHER Need version control of symbols in DE-HDL
, F6 p* P1 I! Z, ]4 y3 S3 I695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions
. W$ u8 }! ?3 L/ D t7 T1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List
1 p: n- R0 o c1357843 ALLEGRO_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate
) Y: N# w/ c: g0 [$ A" B! K; A" `1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees
' k" i6 v- G8 E7 B- o/ V# v4 [1 }8 ^1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias7 X) r! e) U4 v& J( y$ z
1412635 APD DATABASE APD crashes on saving design
+ h: S: B1 \* \. d6 \) B7 j1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices
5 t( \, G* r/ G2 j8 I$ K1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation5 Z* R2 e# w; Z4 c: r
1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.
3 U7 ~/ u% d1 i; ~% I) L0 s/ }1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50' j( v/ ~1 F7 y$ |- e: m
1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"
/ h0 J2 r# g. @$ }5 ? q7 i1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module
5 y7 F1 v4 I3 ^6 y2 _1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated- D; [3 j* V, I3 p' `9 v
1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output
% `& X7 [* a6 y8 B9 c1 ^0 x1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification
% V# |: K' B8 w6 @* F, s5 [$ w1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text., v6 d6 q! f0 ~8 l) p, y
1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets" E: t; D* i/ ^5 q
1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor
& G1 W! s9 `/ T+ E& b1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow! K& ~7 L I1 y
1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed
* H. I* s5 x( F1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board
( [' \6 M6 A% U5 S( }1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks& X1 ]- v% ~4 G8 H- P" U
1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports& D8 g1 Q5 G0 J+ U
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC% b/ s, M2 ^7 X+ c: H% z
1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary6 G# m/ B' Q- j. Y6 M
1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.# v% a3 w9 k$ p+ o
1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 12 R1 L9 y s7 A- r$ }8 g
* v, v! I: c7 P1 N b
; z4 l& @* h$ R& I' t
http://pan.baidu.com/s/1mg28zJM6 L& }/ O# P8 u" ^$ f% `
|
评分
-
查看全部评分
|
[复制链接]
/1 
发表于 2015-8-3 11:54
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
