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Fixed CCRs: SPB 17.2 HF022
! u1 i o4 b# O7 B1 a) v06-16-2017
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CCRID Product ProductLevel2 Title/ A1 r) ~/ V6 H/ l, a% g
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1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'% P8 s% R" a& F6 |1 l+ x \+ t
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager6 g7 r8 ~6 Y# I6 r7 \' A9 H L( [, V) n
1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager# G3 D, o [7 |/ |- Y' Q+ u
1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager: ?8 U; S1 a, l; _4 [
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications$ O+ {# Y' @% g( F5 R. L
1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager4 v, c+ B2 X" e
1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor
1 @+ x! a: y. s/ @% c1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it
0 |1 H$ a& m. x, u S9 x+ o1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
/ ~, i9 i& D0 ?9 E1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor, S7 D; {0 X0 Z6 @" C- e' N, a# i7 z
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
0 R3 t& E8 f2 `2 \$ a% R" ~. k1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps5 n2 U1 p/ V3 v. E, W6 t: t
1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
& R* K: S6 ?5 \% @5 T+ Z1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.! W. ~2 H0 G, x# V3 R/ e' |
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run2 c* R( [9 ?7 H5 h8 L
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor. @% Y( \- n3 C& w- X# F
1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture
( o+ c( X% S2 P! N9 T4 A+ j1 ^+ I1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool; N5 K' S( S0 d) F' z7 U2 Q4 r
1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic( K1 ]% j0 s, w& }& o
1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
4 b; {- C0 ~( P6 M" s1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails9 @ |9 ^9 r. w$ p p( o& H1 {
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016- I! H' l! i; t9 u* _3 W) @
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor3 F; Y) u B/ |0 \9 g1 N m
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias
4 j' k, I+ h" ]0 I! i& w1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016. }- i5 P+ c+ t* ]8 ~
1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
+ F+ ?3 `+ t' ` |. e3 M) I3 L1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point
0 b9 Q% z+ x @4 q; P1727206 APD SHAPE Merging two shapes results in an incorrect shape3 i* B1 Z" V7 z* Y8 f% u
1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL# T0 W4 H! `' D# t( `
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
8 t$ \2 X; g# C7 r5 l; \& n1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)2 P6 B7 q% {5 v7 O! G% ]
1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
5 }0 t; e3 A0 I7 Z" P. k [. ]1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option$ r$ H2 @1 m+ R5 K) u
1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting% x8 n# G6 p' V$ s8 i
1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
3 Y6 u# m W1 e5 Z9 R/ r1719105 FSP GUI Tabular sorting not working in FPGA System Planner/ x# N& P8 Q; |; W& v0 t
1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor7 L1 M3 B8 x: S: Z" e
1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file- D& `5 u! {6 u% V5 X( v
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window2 V" ]# D6 D, T2 M) W {
1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files! ]! l9 Z) O) |
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check |
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发表于 2017-7-2 18:36
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楼主
发表于 2017-7-2 19:07
