|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
: d7 F$ t4 V Z, U& X$ y) x' Zinput clk,rst_n;8 Z* k/ W2 v' R4 ?% @
output [7:0]led;
! _' s* D4 I, t& Y( y. y! b" Boutput [5:0]led_seg;
- }* |% M. g! E! [5 Foutput SOS_En_Sig;
8 f0 `9 T" N+ o9 u* [& Sparameter seg_num0=8'hc0,/ ^( q: w: H9 b$ }: |7 g* a
seg_num1=8'hf9,+ j* J( \. c. H+ p% K
seg_num2=8'ha4,1 S5 d8 E6 ~9 [. A
seg_num3=8'hb0,: u) X) u; [6 X" I9 q) V" ?
seg_num4=8'h99,* {6 @ O8 d% c, X5 m
seg_num5=8'h92,0 s r# b& l0 V5 P* ]# q! ^' L
seg_num6=8'h82,; r% l# R9 X0 V" x- H; z+ L
seg_num7=8'hf8,- v; ]; |, d! l) ~& ?" K. M. P
seg_num8=8'h80,
% [$ i9 G; |4 Y% }, L seg_num9=8'h90;9 F. W: K. O' l2 {' x" k1 n
parameter seg_en0=6'b111110,
, f w& E8 J2 M' i; T% J, q seg_en1=6'b111101,
% ]9 ~- `: Y, [+ _ seg_en2=6'b111011,5 S0 G* C8 z" t) S e: N3 A
seg_en3=6'b110111,6 R, C2 v( j, q7 o8 V
seg_en4=6'b101111,5 t5 Z6 L6 z1 _/ y
seg_en5=6'b011111;
" x' q% \- j+ b7 C1 Qreg [26:0]count;
; [- H: H) a0 W$ jreg [3:0] count1;, l1 g* I# D8 c, h5 H
reg [3:0] count2;6 g/ e' W& q' @* x0 h
reg [7:0] led_reg;
. E, q7 u! [' a& v8 Nreg [5:0] led_seg_reg;
7 A2 m- B$ \4 k( q1 halways@(posedge clk or negedge rst_n)( g9 S( M( o" l+ d1 D0 b3 k
if(!rst_n) count<=27'd0;3 T+ z! L6 U: x6 P4 W
else if(count==27'd49_999_999) count<=27'd0;
- d$ r0 O+ ] Melse count<=count+1'b1;+ |' B9 S7 Z( e( N+ N0 R8 ?
wire clk_div=(count==27'd49_999_999);/ O1 N1 k" w* Y) B, N
always@(posedge clk_div or negedge rst_n)& b( I' T& v7 p/ U' x- E
if(!rst_n)
# R, I7 F. z0 G1 r5 B. |+ F5 sbegin9 m9 d& Z1 a; x. J
count1<=4'd0;
8 [1 F& i1 J7 Z& c* L- p; t* k1 Qcount2<=4'd4;
; a6 l4 w: a2 f+ S2 S$ n4 ]end
0 S5 E4 {9 \* c% o3 ]# Relse if((count1==4'd0)&&(count2==4'd0))
3 S: u* K* X( K& X; Gbegin
, S# l1 m9 z) G! d9 u0 T ycount1<=4'd0;
; e& g6 A, s8 Y* Xcount2<=4'd4;
) n' ?/ S4 K3 R5 t+ z) X! v' Aend; @3 v9 t2 z# q( u/ X. h
else if(count1==4'd0)7 X8 r. D0 V: d* b1 T( a
begin% `- C \0 J; ]- n$ D% ]6 @
count2<= count2-1'b1;, ?! L2 y4 T4 r9 t# ^
count1<=4'd9;
1 `6 O3 q a6 H: X3 rend: l+ N' i2 F) S2 D; J
else count1<=count1-1'b1;9 X* I1 O- G* Y6 Z$ \" z# Z
reg [26:0]count_1ms;//8 z- _5 n! h; ~, x" V
always@(posedge clk or negedge rst_n)
4 ~! o8 c1 J5 y. y9 j5 T& |if(!rst_n) count_1ms<=27'd0; $ m% E4 ?3 n2 X- L+ a- S" K
else if(count_1ms==27'd49_999) count_1ms<=27'd0;$ i$ C f1 n+ a: E6 Z& Q8 f
else count_1ms<=count_1ms+1'b1;+ M. _4 K( Q# ]% b0 y
wire clk_dis=(count_1ms==27'd49_999);//
0 Q. t/ A$ l/ z# U// X& f, [3 M. e9 ^, Q, O( h6 x2 v+ H( a
reg [1:0]state;' L9 s0 z4 P) M0 B) @
always@(posedge clk_dis or negedge rst_n)
7 q* f. h' [: `$ {; ?$ `if(!rst_n)2 @2 m9 U8 R3 ~
begin& E; D1 M0 O4 |5 `( w$ I8 @
led_reg<=8'hff;0 r% a& M4 P" O
led_seg_reg<=6'b111111;! @0 e7 O' b6 w2 a4 _2 M+ X
state<=2'b00;
6 |/ a7 C% u1 o1 y$ ]end
$ g2 `- B+ ^- Y2 jelse if(state==2'b00)
% N& }7 d5 ~% r$ u bbegin' F, B0 X" y/ C
state<=2'b01;
0 x% ^4 H% Y$ M) P- Kled_seg_reg<=6'b111101;- L6 {+ K+ s* |* a: G
case(count2)
I( \0 ?& h9 K; S- A4'd0: led_reg<=seg_num0; 0 f. Q) x) W! C* [# Q
4'd1: led_reg<=seg_num1;
1 E2 Q3 I( e& _ h4'd2:led_reg<=seg_num2; 9 O7 l/ @* v K6 j2 _
4'd3: led_reg<=seg_num3;
; H( a8 V5 n) }5 d+ n7 w9 b0 x4'd4: led_reg<=seg_num4;
' F0 R! p' P9 m1 L: n6 g4'd5: led_reg<=seg_num5; 3 q; i2 H1 L Q' _ J2 R
4'd6: led_reg<=seg_num6;
5 u; E1 h9 I" U+ B3 t4'd7: led_reg<=seg_num7; ' B! s; h# g- P0 L2 |) d
4'd8: led_reg<=seg_num8; % b3 w2 Y0 N' r8 F \1 M
4'd9: led_reg<=seg_num9; # H0 [8 i( c* ]
default: led_reg<=seg_num0;
) F1 R( }' `) v. X3 j/ Y6 ]6 Gendcase' H" Z4 r q" a, F, I& ?7 w
end
Y3 t0 l0 t R. D7 y/ \: f# `else if(state==2'b01)
% F! v: k9 ^, }( h: [& Pbegin 6 e( a' }0 ~* ~ S4 N/ ]" {
state<=2'b00;; i! z+ p# }4 D7 h' m7 X- h
led_seg_reg<=6'b111110;
! w1 u3 R1 E6 Y: ^& v8 R8 s5 Ccase(count1)# M) \3 O* l# O4 F- ^
4'd0:led_reg<=seg_num0;
+ k( e |' c3 G4'd1:led_reg<=seg_num1;
% n8 `1 w3 D7 ~6 F; [% l; y) e n4'd2:led_reg<=seg_num2;* i: G L+ W7 w0 W5 d
4'd3:led_reg<=seg_num3;+ y, P4 N: ?& F0 S* g
4'd4:led_reg<=seg_num4;8 ` O3 ~$ m/ [7 k* e# N- J* e
4'd5:led_reg<=seg_num5;8 X; U- h" Y5 B& j
4'd6:led_reg<=seg_num6;
$ t, ]! _1 ^, q0 f( @) c8 d0 T7 t: T4'd7:led_reg<=seg_num7;$ M: V9 \! A5 `6 `# h
4'd8:led_reg<=seg_num8;* C. X w; k2 {# y
4'd9:led_reg<=seg_num9;- `3 V$ @: Q% f+ w9 C
default:led_reg<=seg_num0;
8 e* R2 Z1 f1 `# qendcase0 q3 ]) c7 S1 x: X6 p7 Q
end6 t" ^. B D$ w* Y. B( L
reg isEn;
' M3 \. i4 Z* _& u& jalways@(posedge clk or negedge rst_n)
1 ~3 u+ Z4 c6 F6 u) ?0 Qif(!rst_n)
# \+ _: F, P$ F6 Q3 |' |begin9 _# j! c7 R2 o
isEn<=1'b0;; _" f' g+ a9 O+ U7 y7 y
end; I: Q a. e- [. b
else
) \3 d0 g) S: Q- }& B* f0 K$ bbegin
2 o$ Z R+ I% c* L# j, JisEn<=1'b1;9 P4 [: K4 u7 p3 N9 C) v
end8 Z7 c8 ]* B- A) h% g
assign led=led_reg;
$ N7 P) \+ N' G6 T7 ^1 [3 @) f. h) _+ oassign led_seg=led_seg_reg;; `+ l' z, {, o, l
assign SOS_En_Sig=isEn;: @9 j. Y1 R. u. u# A
endmodule
' ]% u( c0 H" }; f+ P: d( \4 q. j8 ~/ g/ i2 L) ?
|
|
/1 
发表于 2016-4-13 18:01
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！