求救—谁能帮忙改一改

zhong0985

library ieee;
& B/ b9 K; u2 I3 Q. ouse ieee.std_logic_1164.all;
( {* N; z. e8 b( U5 ~5 E+ u" ouse ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
5 _2 U/ Q  \8 D) k7 b% a( nentity hour is
7 S, N6 Y& c9 a- M port(clk_h,clk_t,tp_h,res_h:in std_logic;
  hset:in std_logic;
  sig_h:in std_logic_vector(2 downto 0);
  din_h1ut std_logic_vector(3 downto 0);
  din_h0ut std_logic_vector(3 downto 0);
" @8 f3 h+ Z# N! S: y  pmut std_logic;
* f* q6 ~/ J* G; n  cp_h:out std_logic);
/ a/ ^2 ]. `0 g( M% _% s  
9 `* a7 Z3 e2 n0 z$ v# kend hour;
2 ~& D4 R2 h6 M  M' r" C7 x. ~architecture behav of hour is
signal clk:std_logic;
9 X/ I  h1 b$ d; lbegin
- K7 w& k. Z& ~  J  t4 n. w7 F/ U    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
- s, F7 ]1 j' D9 C     variable co1:std_logic;
7 u. k$ J8 }- ^9 ?     variable co2: std_logic_vector(7 downto 0) ;
: ^" t  H/ U8 [( [4 h   begin
    if sig_h="001"and tp_h='1' then clk<=clk_t;
   else clk<=clk_h;
   end if;
    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
            end if;
            if  cq2="0010" and cq1="0100" then
6 ^4 A8 P( s* r& I    cq1:="0000";cq2:="0000";
% L7 W' a' R6 X6 D: z- a    co1:='1';
8 ]0 k% r" X) O1 G, Q7 ?   else co1:='0';
      end if;
      if cq3="1010" then
      cq4:=cq4+1;
; x. I# O& S3 J# o6 f. i' @3 {      cq3:="0000";
) m; |+ s; b6 p/ a5 G$ `    end if;
6 w, ^4 R' z% r) e& T4 k+ Z$ I) a6 Y2 |   if cq4="0001" and cq3="0010" then
         cq3:="0000";cq4:="0000";co2:=co2+1;
" j3 a& g8 y2 m  n      end if;
0 M* x. _: f5 g! ?8 ?    end if;
5 Y  s1 h& y+ L4 u  if hset='1' then   
          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
6 E4 g, X! c8 G/ L3 z7 t2 d( c  I" d         else
, O; s* P! J7 n4 i& \           if co2(0)='1' then
             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
' T- e3 [! E. C  K- ?# _( ]             end if;
0 S( U$ \6 _- c# }- X3 B             pm<='1';
# m6 i8 X% X8 X$ [3 A            else pm<='0';
- A5 J0 N9 {$ z8 \& x# Q            end if;
: W1 R& b# C" S0 U8 ~; T            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
/ b# ~: F: U: R! v$ s              else cp_h<='0';
: Z0 M# L1 _. _, F8 `             end if;
           din_h1<=cq4;din_h0<=cq3;  
! _0 [5 W, W" ~  K- l        end if;  --12/24转换
  
; K) K' k# E: _6 J     end process;
end behav;

zhong0985

报错：
2 K& s, C9 u1 w- tInfo: *******************************************************************
& {4 I9 q) S! p( h" {* v. Y1 ]Info: Running Quartus II Analysis & Synthesis
        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
        Info: Processing started: Sat Oct 31 17:04:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
! o. w8 O; l5 ?Info: Found 2 design units, including 1 entities, in source file hour.vhd
2 M& L$ b/ o0 z: c  W6 s! C+ i% d        Info: Found design unit 1: hour-behav
        Info: Found entity 1: hour
4 ^' d4 s2 B  n8 A  \/ w: y7 dInfo: Elaborating entity "hour" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
6 ^* M! O+ c' g7 \$ G" ]Warning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
, w5 g9 ?( F$ V% N4 ~Info (10041): Inferred latch for "pm" at hour.vhd(20)
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
$ Z% o# H( G. b% X' j  n: [Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
! ]% i6 F: d: y$ L  O7 [6 a8 z: Y; a1 hError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
9 i% T0 _# G  wError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
Error: Can't elaborate top-level user hierarchy
5 X/ g8 u; @4 dError: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
. Z0 {' ?: H4 N3 K        Error: Peak virtual memory: 184 megabytes
        Error: Processing ended: Sat Oct 31 17:04:04 2009
" W& A* R9 o4 R# g        Error: Elapsed time: 00:00:02
        Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings