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在网上寻找数字地与模拟地的英文材料;9 x! f9 a2 C* W- M, i
无意间浏览到一个国外的的CPLD/FPGA论坛,点击进入+ s9 f! v- p/ |- g3 f5 I. O! d2 N
发现了有人求51的IP CORE,在回帖里面看到这个,所以下载了。1 N, E8 H' j, e1 F, k6 }1 m
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% ]: Y9 H* j* |6 v4 e@: mc8051@oregano.at# B Q8 I# [( A6 n5 {- @
W: http://oregano.at/ip/8051.htm
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************************************************************0 m" S7 W/ c% z; Z1 Z* r
This is version 1.4 of the MC8051 IP core.' i# \8 [* U/ z: k: T! [, C, u
November 2004: Oregano Systems - Design & Consulting GesmbH
* \, z2 F' O( K9 g4 V q5 `9 l============================================================
& ^+ d1 y7 |2 s4 bChanges:4 \+ n# f7 Z, }% i& z5 n$ A. \* T
- corrected behaviour of RETI instruction handling, ^4 h/ |& f5 T$ U; b. k$ {+ _, P
- added synchronization for interrupt signals' O+ M2 c: u+ b8 j9 U) Q8 I0 l
- corrected timer problems0 z2 Z" i' c/ e4 D' w& k& [
* r, H$ O$ b" I# x0 u) P************************************************************
2 g& r; A8 H9 }/ UThis is version 1.3 of the MC8051 IP core.
( g }) C' _1 y: ^/ [$ YSeptember 2002: Oregano Systems - Design & Consulting GesmbH
; G5 U" _3 m, x* N: N9 `============================================================
8 x$ }* F1 w* q5 k+ j1 o+ ]Change history:
/ C# `7 k" h/ D# U/ n4 N! P- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.
/ N3 A6 b6 Z/ Q5 n- Corrected problem with duplex operation in file
- \7 W0 c: W1 A( Z; J) I1 N mc8051_siu_rtl.vhd
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9 Z) U1 I1 ?- I E- J% n# a************************************************************
0 j1 z% F. ~$ c! @* x# ^& p/ {2 |This is version 1.2. of the MC8051 IP core.7 f4 a% ]6 z4 K/ Y$ K" l( E) v
June 2002 - Oregano Systems - Design & Consulting GesmbH( d; b1 M: z) ]/ z
============================================================
" P* V. I! w4 B. Y+ g, zChange history:
7 i0 e$ G6 b( Y0 R ^8 r- Eliminated the scr subdirectory form the distribution.3 ^. b* v8 f4 \
- Improved documentation.4 c4 b" X+ O u, [) ]5 x; u
- Corrected several bugs in the source code (see the' |4 [5 j( E1 Q! U" p
website for more details).; x; ^9 u x3 `% w7 I2 G
- Improved the testbench with respect to the I/O port( z E* u8 k" e
behavior.
5 {% k. D9 y) d! f* T, Z- Enriched the msim directory with the assembler source7 ~! e" I B7 b! @3 @
code of an example program.
( U. h$ t& e7 [, t5 o! O- Provided the source code of a Intel hex to binary
x7 ]! A( A X1 ?7 ~$ z! _ @! p textfile converter to ease simulation of the user's
6 O) h) x& c& Z: N assambler programs.
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************************************************************
; v8 |# f2 N# ^3 Y2 XThis is version 1.1. of the MC8051 IP core.
' H. B9 N) d2 X1 Z7 f; R& }Jan 31st 2002 - Oregano Systems - Design & Consulting GesmbH+ B7 F9 _& k6 Q6 q
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7 g; b' L, L$ R" ~/ c7 S% v下面是里面的部分VHDL
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library IEEE;
, W' g2 z# [+ m$ nuse IEEE.std_logic_1164.all;
# f6 [6 _( i! u: _; Yuse IEEE.std_logic_arith.all;
- K7 j, ?- X* L; [2 Elibrary work;) T) F d( n7 D" N* s) p9 x
use work.mc8051_p.all;7 c. x3 j% Y: a
% B) z% x4 a: m0 A, x& p-----------------------------ENTITY DECLARATION--------------------------------/ C+ R7 Y2 c- h, k' Y
entity addsub_core is
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generic (DWIDTH : integer := 16); -- Data width of the ALU
0 a: G* S h( k. `8 c/ o' n) b8 c port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
1 K: T8 O/ o( q7 K0 J& s opb_i : in std_logic_vector(DWIDTH-1 downto 0);8 [" k2 J E" f
addsub_i : in std_logic;: W1 I' c, y, n
cy_i : in std_logic;6 i8 p% e6 h2 s# k/ g$ n" ?
cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
. u0 h' r, `3 S# y% A% u; X* L3 T ov_o : out std_logic;" v% g+ \+ ]% T# b1 J% ]2 {
rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
% [- R& w G4 f& a$ l
6 k" g, i% z$ E: g: S+ \7 eend addsub_core;) W7 U5 h# p" _# q
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1 [) y, K( C3 Dentity mc8051_alu is
( a9 z) |; ^3 o) v- Q/ W b( Q. W- o* E generic (DWIDTH : integer := 8); -- Data width of the ALU" \; | t+ D2 m6 q$ K
port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
$ p b2 i) w( A" i H( p% u ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
9 X" ? g* a+ t2 T% b" ^* A acc_i : in std_logic_vector(DWIDTH-1 downto 0);
8 F; d9 K* H9 [6 R) D cmd_i : in std_logic_vector(5 downto 0);
& X, W( {. Z% K! S3 m cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
; z2 g6 X2 \5 z/ Z+ ]% a ov_i : in std_logic;
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new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
; t% s9 Z8 e% L7 {' M new_ov_o : out std_logic;
6 c' s- `0 y1 S4 e" J result_a_o : out std_logic_vector(DWIDTH-1 downto 0);; w9 |% }" l0 c- m- o6 z1 e
result_b_o : out std_logic_vector(DWIDTH-1 downto 0));& ~& I, L k! Y T
9 h: X0 v8 I' A# G, F( Fend mc8051_alu;; H% K# ?0 @# K6 C8 _2 x! ^: P
--Inputs:, A" P: y; e& [7 y& Z
-- rom_data_i...... data input from ROM; h4 H0 A) h, T) z; j& U
-- ram_data_i...... data input from RAM: i4 N! C6 K+ ^+ s/ A8 Z' _
-- acc_i........... the contents of the accumulator register! K6 ]) l7 m& l. R( p
-- cmd_i........... command from the control unit- W% L' M; v T' W2 @
-- cy_i............ CY-Flags of the SFR( g0 P/ }' b9 `. k
-- ov_i............ OV-Flag of the SFR
6 V* g4 v$ k7 e--Outputs:
5 F, p- d3 k2 L/ v$ d-- new_cy_o........ new CY-Flags for SFR
4 J0 t8 v0 [8 T! \- N: t% g" R-- new_ov_o........ new OV-Flag for SFR- H5 \2 B0 o# k3 T
-- result_a_o...... result5 v7 Y4 Y d% `+ I
-- result_b_o...... result
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architecture struc of mc8051_alu is
" {5 g# t( I6 o- s signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);2 q. t" c6 M3 Z6 m
signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);
9 T4 }6 g* q- [" z9 G" t& Z$ S signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0); O1 m9 m4 e, y6 B
signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0);
" k$ U4 c" y0 \& t; N, \$ \+ W' A signal s_alu_cmd : std_logic_vector(3 downto 0);
% s( n# ?9 {+ p) i2 [ signal s_dvdnd : std_logic_vector(DWIDTH-1 downto 0);
: b$ |; v8 f6 @! ~) j$ p" D; d7 L signal s_dvsor : std_logic_vector(DWIDTH-1 downto 0);% p1 O, Q; J& x9 P% J
signal s_qutnt : std_logic_vector(DWIDTH-1 downto 0);# i( s: v$ I4 g
signal s_rmndr : std_logic_vector(DWIDTH-1 downto 0);& W7 \3 e+ B& [
signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0);
! u! x+ H/ R e- L4 | signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0);
* }1 P$ M8 p5 O signal s_product : std_logic_vector((DWIDTH*2)-1 downto 0);
0 v: m! P6 ~; b* |- {7 c+ i signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0);
9 x" ^% a7 H. ]8 a* `6 G signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0); }& {7 c X8 @7 ?) u: k8 W
signal s_dcml_cy : std_logic;
9 g+ M: H: H2 Y6 j% Y signal s_addsub_rslt : std_logic_vector(DWIDTH-1 downto 0);0 P2 G( t3 E t9 F1 y
signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);7 {0 l4 E7 Q4 ~; Q& L7 o0 H
signal s_addsub_ov : std_logic;
% m+ L7 c. Q; K( [# G' ^7 ] signal s_addsub_cy : std_logic;
9 d. L/ h! k0 O2 [% s2 Z, I+ x% c" t signal s_addsub : std_logic;
$ X* {: C1 G5 m4 {* F5 ~/ n$ c signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);" z2 {3 j: e# x1 {
signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);
( Z6 p& ?& p, z1 B5 _0 w1 ubegin -- architecture structural; y3 [# \2 q! H7 i( ^
i_alumux : alumux
' f* R! P0 T; [3 F" J0 l generic map (; g/ I# X# G: }* o- m A
DWIDTH => DWIDTH)
! p2 f: U1 [" L3 X port map (
, N; O k$ Z k+ ~ -- Primary I/Os of the ALU unit.$ F+ ^/ L6 v6 Y3 n5 t, D
rom_data_i => rom_data_i,
8 f' Z3 k" v0 m5 J! | ram_data_i => ram_data_i,6 H; f0 d+ w) k, H
acc_i => acc_i,
, Z" r- Z: W. H. M% y D) Y cmd_i => cmd_i,. [! H! g+ `% ]! O* A% |8 x! r
cy_i => cy_i,
5 v& r- ]' g3 \. H! W" O6 P ov_i => ov_i,' O4 c" e8 O9 I! d8 {' }# M
cy_o => new_cy_o,
2 O! y/ u' w( s& C, c+ P/ I9 A+ |9 g ov_o => new_ov_o,
# i8 ~. k7 l! N1 [5 E! _2 [8 q result_a_o => result_a_o,$ Z+ Y9 y3 e6 B) c5 a* p% p/ H+ c" z
result_b_o => result_b_o,
+ C9 T8 Q/ r8 ^1 R) E' V1 A -- I/Os connecting the submodules.
2 s" w& S: L* P: N; o$ Y result_i => s_alu_result,$ i( {1 }( f+ e3 k/ g3 \- o- C
new_cy_i => s_alu_new_cy,3 D) c3 X, d/ r: h$ }
addsub_rslt_i => s_addsub_rslt,
* A8 T& U# z8 e a addsub_cy_i => s_addsub_newcy,- k8 o( U! {, z$ k
addsub_ov_i => s_addsub_ov,
: R& v- u" n( V; e6 u8 ?( v op_a_o => s_alu_op_a,
; C* n" g: T$ |9 A! M# J! L op_b_o => s_alu_op_b,9 ~# N; N3 E0 X& {" \
alu_cmd_o => s_alu_cmd,) Y* B: g5 s3 ^
opa_o => s_addsub_opa,
* H! h. c$ B" v opb_o => s_addsub_opb,3 l2 F' ?2 m$ Q/ M8 V5 s8 a
addsub_o => s_addsub,
: x/ o& w0 j3 M addsub_cy_o => s_addsub_cy,& i. [* s8 k; @8 O y1 ?
dvdnd_o => s_dvdnd,
- I1 ?$ u5 y6 k N8 r+ a3 j( _ dvsor_o => s_dvsor,
9 u" u; i) p9 m qutnt_i => s_qutnt,
; e, L# ~' V3 P4 J" l/ v# H' p rmndr_i => s_rmndr,
9 W" C" s3 P# u9 d/ o mltplcnd_o => s_mltplcnd,
& Y8 |4 o# Q; F4 |# l+ R mltplctr_o => s_mltplctr,1 K y, d- i( b
product_i => s_product,
l1 E% Z3 ^; @/ e9 l7 a dcml_data_o => s_dcml_data,
3 M5 L: n. S3 [0 U C( `8 ~" W dcml_data_i => s_dcml_rslt,; X2 }1 C9 |2 |0 O
dcml_cy_i => s_dcml_cy);
3 G0 h% u3 t; m E i_alucore : alucore* q% X7 Z1 i6 m; [9 E
generic map (
: x8 Z! B; j l$ \; J) |/ d% p DWIDTH => DWIDTH)
+ V1 h4 T# i% |+ j$ y port map (9 ^8 p( q2 D5 l4 [6 K
op_a_i => s_alu_op_a,( g: J, h: ^/ r/ U
op_b_i => s_alu_op_b,
: f, X. J; d A: p* V! p1 \/ |' S* L' o alu_cmd_i => s_alu_cmd,7 u3 g Z, {3 t+ p+ y! i
cy_i => cy_i,
$ p! d4 y4 H* c9 w! W" m( k F5 M K cy_o => s_alu_new_cy,
! T* i, i* f' G" X- J/ E4 O7 p result_o => s_alu_result);3 y% d7 q8 s. ]+ t T
i_addsub_core : addsub_core
! E% M2 v. t4 V7 s7 W generic map (DWIDTH => DWIDTH)
) ?& t: u& B% u) z3 |+ j' A port map (opa_i => s_addsub_opa,1 ` ^8 _& J" M! C* J: y* q: p; c
opb_i => s_addsub_opb,# Z" R/ m4 o5 A
addsub_i => s_addsub,
~6 D1 X E$ t: E cy_i => s_addsub_cy,6 L5 r' s, g5 l9 T% B; ]: t' R
cy_o => s_addsub_newcy,7 i, w( Q' \% x" c) Y
ov_o => s_addsub_ov,
2 K4 b* y& T! H1 _/ | Y rslt_o => s_addsub_rslt);4 v* v# R+ v. O) Z X1 l
gen_multiplier1 : if C_IMPL_MUL = 1 generate' q. M. m% T9 k; A J }
i_comb_mltplr : comb_mltplr7 E6 n8 \% i; c5 S; r- l
generic map (
+ x- Z* l1 Z/ i! f DWIDTH => DWIDTH)# H# e/ X8 X2 I) w$ n0 E
port map (& V$ a# d! [0 F1 j2 K
mltplcnd_i => s_mltplcnd,
* o8 M. a' \3 L* u mltplctr_i => s_mltplctr,. d1 `( g" r8 r$ \
product_o => s_product);6 _8 z9 Y/ E* p, o: n1 G& z* U
end generate gen_multiplier1;1 N2 g# X) D* _7 Q3 y9 b
gen_multiplier0 : if C_IMPL_MUL /= 1 generate
+ [/ U, p6 B$ H s_product <= (others => '0');
1 S( }8 j' a4 F2 G& Y4 G end generate gen_multiplier0; A9 G8 x: N6 K5 U6 Y% b
gen_divider1 : if C_IMPL_DIV = 1 generate
7 [; }6 }* a( k- F$ A i_comb_divider : comb_divider3 w# l4 f P9 m9 V
generic map (
$ k* Y5 M- m: S0 _" ^ DWIDTH => DWIDTH)' i. ?) _7 T4 w/ d4 t
port map (: C) |" K& N( Q! \. \
dvdnd_i => s_dvdnd,, d) n% w5 h4 C, {" e7 {& f. A
dvsor_i => s_dvsor,; q8 N0 N; ?3 v& j4 y5 Y
qutnt_o => s_qutnt,2 S: ~5 e5 d" h8 C# |' M
rmndr_o => s_rmndr);, I. v* `% d; `: R+ K0 M
end generate gen_divider1;4 g! H6 l9 g# i0 D1 q
gen_divider0 : if C_IMPL_DIV /= 1 generate! ~$ `' F& X0 P6 a# A: U. {
s_qutnt <= (others => '0');
; Z; R, \0 y: n1 J! l s_rmndr <= (others => '0');
9 k3 M" H: j1 H8 p+ D end generate gen_divider0;
3 G' X- q& B$ T$ w* | gen_dcml_adj1 : if C_IMPL_DA = 1 generate
6 b j- w6 f' z8 s) n+ b; s: P2 q8 v i_dcml_adjust : dcml_adjust
! V' @: G7 X7 s- a! X( D generic map (" V4 Z- G4 ~$ S, l
DWIDTH => DWIDTH)
* i; K" h+ e5 L$ S9 X; \( Y port map () h& a/ A, W3 a w5 E
data_i => s_dcml_data,) W% Z) c: _/ S1 T
cy_i => cy_i,+ E$ @9 s9 W$ X& b0 B
data_o => s_dcml_rslt,$ D+ S# O+ }5 {, Z
cy_o => s_dcml_cy);3 o E& b X7 y
end generate gen_dcml_adj1;1 [9 v6 [& r% c$ F5 L- F4 H
gen_dcml_adj0 : if C_IMPL_DA /= 1 generate5 C* b* {2 [! C9 j' U
s_dcml_rslt <= (others => '0');
* g3 W' G) f/ e s_dcml_cy <= '0';
# e1 p9 F- Z, Z end generate gen_dcml_adj0;
1 Z2 H0 {7 U1 R3 Q& M/ c* P% i& eend struc; |
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