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在网上寻找数字地与模拟地的英文材料;8 W- }/ p4 I7 r- Q$ V
无意间浏览到一个国外的的CPLD/FPGA论坛,点击进入
2 _) [) f; E9 E; Q" W发现了有人求51的IP CORE,在回帖里面看到这个,所以下载了。- K6 Y" Y* B# s) L, d! r
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@: mc8051@oregano.at
$ g. ^/ h, Q7 i! a. ?6 M! Z& QW: http://oregano.at/ip/8051.htm
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. ^& z* e0 t2 T- U. ?************************************************************
) T* S, x; V& [* { j" p& F3 M7 XThis is version 1.4 of the MC8051 IP core.
: ~3 { q5 \4 ~November 2004: Oregano Systems - Design & Consulting GesmbH. S8 E, p$ {* ~0 j
============================================================( F& {4 F1 A s! ^ M* C
Changes:0 {% x- J) E2 K
- corrected behaviour of RETI instruction handling
% |3 @. r7 K7 y+ L- added synchronization for interrupt signals
! L! I! n a( Z4 P6 s4 \- corrected timer problems
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) b' _* H* ^$ ?8 X, }) n. B************************************************************" \5 z1 `! \3 z0 ]) O
This is version 1.3 of the MC8051 IP core.
: `( g! `8 k8 V& eSeptember 2002: Oregano Systems - Design & Consulting GesmbH3 B3 W) I U5 ?) r' R/ f2 @
============================================================+ A3 }* j8 {* X" y+ }8 l
Change history:6 N( N% H) I) M7 a
- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.) Q7 L4 c+ ~8 T! y- C/ O
- Corrected problem with duplex operation in file
1 {" ?8 x) \) F mc8051_siu_rtl.vhd
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************************************************************9 |6 h h' T6 L9 S# {
This is version 1.2. of the MC8051 IP core.
3 K$ n3 e% P! @, b; {June 2002 - Oregano Systems - Design & Consulting GesmbH# h* j" G+ `7 H% _
============================================================3 {( ~6 _+ B7 L* C. e8 u! w1 u
Change history:
/ q: S9 v! S3 Q3 J- Eliminated the scr subdirectory form the distribution.
% s, k& s$ s% k- \ _- Improved documentation.
; X/ U; c: d4 [8 P# r- Corrected several bugs in the source code (see the j% b/ k" X/ V! Y( ^
website for more details).) H/ o5 }7 L" K! s. f% S: Q
- Improved the testbench with respect to the I/O port
& x$ R+ R, \$ S behavior.2 r, v" o C2 k% q: S% B/ Q: x
- Enriched the msim directory with the assembler source
2 j: o& Y; G) d7 {0 u+ R2 l! ?$ y code of an example program.
) E( e2 G# Z9 n6 N c M9 J- Provided the source code of a Intel hex to binary7 [. C4 s" }3 |
textfile converter to ease simulation of the user's0 w0 E' A9 j k5 u5 w! R7 U& F. Z8 c6 c
assambler programs.
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0 ?9 E2 a/ g k; L' k- t/ b* m************************************************************4 _; u# h/ c n- F% }5 z
This is version 1.1. of the MC8051 IP core." Q4 _7 w5 e0 h7 S) @6 W* |
Jan 31st 2002 - Oregano Systems - Design & Consulting GesmbH
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下面是里面的部分VHDL
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library IEEE; & a5 b4 n1 Y; }4 C9 ? b
use IEEE.std_logic_1164.all;
8 Y0 V. R9 g( Ruse IEEE.std_logic_arith.all;
1 y8 E3 z ]7 }* M# p4 Ylibrary work;8 o2 Z& v& D+ r: @+ W# n3 T
use work.mc8051_p.all;
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% F1 {0 ^5 r9 p, c- o-----------------------------ENTITY DECLARATION--------------------------------
4 i0 Q5 k1 e: m! [ jentity addsub_core is. U+ b! T& W2 t1 }* v: A
! v4 u. O& @5 b/ |& V generic (DWIDTH : integer := 16); -- Data width of the ALU
1 a4 ?- @% Y3 l port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
) ^6 J7 t- V* m4 |: ?; Y5 K" I opb_i : in std_logic_vector(DWIDTH-1 downto 0);" l. Q+ U5 B* o; a5 D( O+ r
addsub_i : in std_logic;
. G8 m7 K( K ~3 m cy_i : in std_logic;# Z/ h* b$ P) l
cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);* _4 h% e) O% f: @) l
ov_o : out std_logic;- e) M, y% o3 W- v; a. \
rslt_o : out std_logic_vector(DWIDTH-1 downto 0));; p; W) ?! o, e" a0 M
* W+ N% x0 s/ z$ |: v+ n
end addsub_core;
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# _- N! e) G3 j% Z3 h4 t# K, Qentity mc8051_alu is
8 F% j/ V% Q& w$ A( Y2 f generic (DWIDTH : integer := 8); -- Data width of the ALU
7 J) l9 J u) x: c# y port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
8 _" \3 h9 X7 t& @% D ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
8 K* l3 X# |8 Q$ s" {" ` acc_i : in std_logic_vector(DWIDTH-1 downto 0);
$ \- c/ m# P, ]! U2 A- m9 X% i cmd_i : in std_logic_vector(5 downto 0);0 g( {7 |, y' D$ {) C* {+ w
cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);( t' Y+ }% B6 S q4 x3 x- I
ov_i : in std_logic;+ H4 k6 Y" ]5 }2 r* v. P% v$ K4 z. {0 M
" y5 D$ Y8 M* |7 l new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
1 |- ^, E0 N6 v1 u! {3 y6 A% o new_ov_o : out std_logic;1 Y: b% w0 G! Q7 |$ H
result_a_o : out std_logic_vector(DWIDTH-1 downto 0);3 z5 x" h5 R8 t7 [* h/ w+ N& p# `
result_b_o : out std_logic_vector(DWIDTH-1 downto 0));" l0 v7 c# f. J0 Q3 k5 Q; m
: Y; T H( H7 g& G& o4 Rend mc8051_alu;
% g+ | y' |# k6 e* }. ]- o y--Inputs:
8 B% q% P0 z5 w E! W0 u/ X-- rom_data_i...... data input from ROM1 x6 h5 l! ]& @9 V$ d7 p* I
-- ram_data_i...... data input from RAM5 Z! o i& x. T$ a* [
-- acc_i........... the contents of the accumulator register9 j J3 I$ u' O0 m% i
-- cmd_i........... command from the control unit
1 Y, W0 `: I7 S0 L( v3 F9 R7 r' @. [-- cy_i............ CY-Flags of the SFR
; \! }: u) ^7 X4 V6 T9 J-- ov_i............ OV-Flag of the SFR, m* V0 ^# M' z2 _* k3 ]
--Outputs:/ }( f- i& _; d. y
-- new_cy_o........ new CY-Flags for SFR
; w# x% f; I+ R( w7 O-- new_ov_o........ new OV-Flag for SFR
5 x, D% K+ }* r3 e Z4 ?9 [-- result_a_o...... result
+ R- y! s/ c- S; g$ X-- result_b_o...... result
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. ^4 |* f. k1 l2 Y' O- {architecture struc of mc8051_alu is3 M( }+ k3 V3 p5 D
signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);2 W8 q X# _% c+ t( f& @5 }
signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);( u$ J+ S! C% t0 V2 {
signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0);* z1 j: m& Y/ ]7 }2 ?
signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0);
* f1 O% R* U- o0 U/ I9 ?. A signal s_alu_cmd : std_logic_vector(3 downto 0);; o6 ]# I% M$ S
signal s_dvdnd : std_logic_vector(DWIDTH-1 downto 0);
( R6 l3 }3 P; s) e signal s_dvsor : std_logic_vector(DWIDTH-1 downto 0);! {( c$ p9 P9 N3 M; J) ^ X
signal s_qutnt : std_logic_vector(DWIDTH-1 downto 0);
0 M$ p: X. j" w$ u$ y& r" ]& M signal s_rmndr : std_logic_vector(DWIDTH-1 downto 0);
9 w! E5 f! Q& Z4 q6 ` signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0);! s* h3 k% |1 M+ K* `" [
signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0);
' _8 L* \7 |) H4 U9 m# @ signal s_product : std_logic_vector((DWIDTH*2)-1 downto 0);
" o- p1 g8 Z0 x B$ m signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0);
+ ^' h9 E* R. M signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0);
8 C; R0 W! y6 e3 d signal s_dcml_cy : std_logic;
! G8 O2 Y" a$ b' N signal s_addsub_rslt : std_logic_vector(DWIDTH-1 downto 0);& W" u& f1 Z: h6 b: m# A( h
signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);! ]" O, ?9 w; ^1 r. U; h3 b/ k; ~
signal s_addsub_ov : std_logic;; L8 K7 h! \" k) x/ o! n
signal s_addsub_cy : std_logic;9 h2 m; G! X9 z/ ]% h
signal s_addsub : std_logic;
) M7 N5 H7 J& w' T8 R signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);. p: }1 E7 t+ y3 U9 f6 O
signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);& T1 L% Z: T* d: j+ |* o
begin -- architecture structural
' O5 C+ Z" H9 h- n& c/ g+ Q7 ] i_alumux : alumux7 _! u2 V( l; Z" A0 o: U+ z
generic map (
, |/ J+ N% l1 {5 m1 O$ Z DWIDTH => DWIDTH)
; `- \; A$ _4 w. m9 q% t H4 Q9 `% n port map (
3 k0 V9 G/ U1 q% q8 o. E -- Primary I/Os of the ALU unit.
# p" l; ^! l$ j2 T rom_data_i => rom_data_i,5 ]1 U5 m9 I0 A( i P
ram_data_i => ram_data_i,
; O. H7 [1 w+ o: q& ~' P3 m acc_i => acc_i,1 k# }. I5 s3 B) X+ E7 m
cmd_i => cmd_i,' I4 B, k/ z3 F" S7 J8 ]
cy_i => cy_i,
( K. N; g: n! s2 u# ] ov_i => ov_i,
3 V% @8 c/ w0 }, U" _, S cy_o => new_cy_o,0 N; R4 V6 e' Q- I+ x/ b( c4 ~1 f8 X+ X- X
ov_o => new_ov_o,
4 i8 p) ^3 O6 j9 u result_a_o => result_a_o,2 Y" F q; ^, j4 m3 R" M9 M
result_b_o => result_b_o,* {" q- k. L9 X0 u6 z' L/ d
-- I/Os connecting the submodules." Q5 \% c3 B" m( r: ?( M4 ~! W
result_i => s_alu_result,
0 M4 t; A/ G, J2 V/ U1 b3 V new_cy_i => s_alu_new_cy,8 y9 f, {6 Y1 M6 V) D# U
addsub_rslt_i => s_addsub_rslt,
: P/ G* t- H9 e6 m5 k% ` addsub_cy_i => s_addsub_newcy,
- w( {; |+ v9 i: u8 Z addsub_ov_i => s_addsub_ov,' l) i1 P# m! w
op_a_o => s_alu_op_a,
/ }- L% G( F! z( B9 q, O) ] op_b_o => s_alu_op_b,, j$ P9 K: C# N
alu_cmd_o => s_alu_cmd, M+ @2 \* c$ p- y( S; b; P) U% h
opa_o => s_addsub_opa,
- J4 \" a# \( @ opb_o => s_addsub_opb,* N! P0 H C: [$ P4 L" |: i# P
addsub_o => s_addsub,
" q4 s" u! Z3 i% t addsub_cy_o => s_addsub_cy,; n# c# Q8 _7 L5 i- ?' { ]* F
dvdnd_o => s_dvdnd,
- L' S' b8 n: R w* U% {, q dvsor_o => s_dvsor,! q1 \) [( M. k
qutnt_i => s_qutnt,
: o4 ~# U3 [8 i0 Y: N: y rmndr_i => s_rmndr,- a$ k( E; v( c& X! X9 N- g% d
mltplcnd_o => s_mltplcnd,
+ T" r; T" r4 n3 _ a7 G; R mltplctr_o => s_mltplctr,
( _2 X( V& l! H! N) Q1 ~6 O product_i => s_product,
% [5 \7 Z! A$ ~# k: I0 ^( l$ {- i dcml_data_o => s_dcml_data,
* d; [' D( n- o- j% U ]) { dcml_data_i => s_dcml_rslt,8 h' v. C. h; |- H2 E9 ^ ]
dcml_cy_i => s_dcml_cy);4 x8 H' _1 X8 Z& j. B
i_alucore : alucore, B( Z8 I! h# k* O: t
generic map (8 c$ E* k) o# k
DWIDTH => DWIDTH)
# O" O& D$ w: F; Q/ {% G9 N" ` port map (& }: l; t2 E: k2 J) N. a
op_a_i => s_alu_op_a,
7 T- C, {! {* r6 S6 d op_b_i => s_alu_op_b,# ^2 i! m9 W: V: s* `& U
alu_cmd_i => s_alu_cmd,0 ^' J/ B [3 a2 h
cy_i => cy_i,
/ l3 C- H4 ~2 X8 B: m cy_o => s_alu_new_cy,
& Z& A5 }3 Y* h& V) @ result_o => s_alu_result);# d( |& N& y: a: Q; k6 I. ~
i_addsub_core : addsub_core
P; q# J; A" `* A# a+ x, Z- |: l generic map (DWIDTH => DWIDTH)
" ^5 T/ F. G9 M- f0 _5 y3 ^ port map (opa_i => s_addsub_opa,
+ l9 a) s0 i" J/ R% R" A+ Y opb_i => s_addsub_opb,
% P% e O U* |4 n addsub_i => s_addsub,/ o6 `; F5 o' y1 i- N
cy_i => s_addsub_cy,0 c+ Z. r' p2 W, I3 i/ M
cy_o => s_addsub_newcy,
m" Z1 k8 B- Z, P5 X ov_o => s_addsub_ov,; k: o' W" V, d% a5 a: D0 ~
rslt_o => s_addsub_rslt);. _" j) f6 c- D8 {; ^3 z* {- U3 Y
gen_multiplier1 : if C_IMPL_MUL = 1 generate
4 n$ g- w% E, b/ [/ z. F i_comb_mltplr : comb_mltplr( h, r: u' T9 \" G. n6 H
generic map (
+ y' }3 a5 P, I3 r: p DWIDTH => DWIDTH)
6 K( w" P8 _* _6 f/ ?# Y4 b port map (7 e% R" O. `: x) h, U, C
mltplcnd_i => s_mltplcnd,$ m7 }$ W4 X* l& ?. t9 @
mltplctr_i => s_mltplctr,3 _+ ?& v3 f1 G( ~2 | q* ^9 A
product_o => s_product);- U- o( E8 ?3 a' _& W
end generate gen_multiplier1;- M% A1 n% U, c* a! e+ x; |
gen_multiplier0 : if C_IMPL_MUL /= 1 generate
" `2 |+ k' a% T s_product <= (others => '0');
& W9 s/ ?# R: a$ g I m end generate gen_multiplier0;4 p) k8 {# ^3 P0 D- c/ Y3 x
gen_divider1 : if C_IMPL_DIV = 1 generate- O2 d" J {; a3 _9 W& c3 w
i_comb_divider : comb_divider- L+ K0 }* C0 k1 e0 \$ Z
generic map (
# V/ M) i6 s0 B/ p6 r DWIDTH => DWIDTH)" ] h# T# d" n: M8 p; {! N5 I
port map (
# l6 l5 A: S5 x1 M" F ~6 F dvdnd_i => s_dvdnd,
6 n: F, t: {1 s: D9 M& y% M/ ? dvsor_i => s_dvsor,
! v0 A d+ {, }6 |. |0 H% j2 A! \ qutnt_o => s_qutnt,
3 P3 v8 G6 E6 M, B$ s7 f3 s6 x% T rmndr_o => s_rmndr);
0 T; V) J. g& b, e8 W2 X0 C1 A end generate gen_divider1;+ ?% ?/ F1 X$ T5 v
gen_divider0 : if C_IMPL_DIV /= 1 generate
9 N: D# C# t2 Z1 W s_qutnt <= (others => '0');
: n3 C: M+ _( j! u- H( U s_rmndr <= (others => '0');
/ r: B$ t2 P) v+ f end generate gen_divider0;* X- z# b l8 P# T! t
gen_dcml_adj1 : if C_IMPL_DA = 1 generate
. Y) m5 D6 e9 j2 B3 L i_dcml_adjust : dcml_adjust
' _( F) g4 U G! X) x5 p' x generic map (
" L/ z* s. d7 m. p) b! M DWIDTH => DWIDTH)7 D( X6 E, p* j& s4 w% J, r$ G4 o
port map (2 }2 U9 N H, X& o6 \5 e6 |0 t
data_i => s_dcml_data,
# U6 b* f2 s) D% `& M9 ? cy_i => cy_i,$ E! E1 o" B6 h
data_o => s_dcml_rslt,/ N) ^$ D- w. Q
cy_o => s_dcml_cy);" j% ~. T# E/ H3 ~% u1 c
end generate gen_dcml_adj1;
$ R2 m6 ?; W2 ^+ Q( y5 c gen_dcml_adj0 : if C_IMPL_DA /= 1 generate
5 V+ l8 e4 ^0 p4 M. ]2 O s_dcml_rslt <= (others => '0');: S/ m- l; X2 z/ G2 d k. U
s_dcml_cy <= '0';
p" y; p: b( Y) g( @ end generate gen_dcml_adj0;( M. M+ }, V# d0 t7 P- X; Z8 ^
end struc; |
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