SPB 16.6 從061到071版的補丁內容

jacklee_47pn

DATE: 05-28-2016   HOTFIX VERSION: 071
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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0 C( j* _+ }) u1452838 CONCEPT_HDL    CORE             Apparent discrepancy between Bus names and other nets
2 G; C, Y7 ?7 Y3 u5 ?, d1469146 ADW            LRM              ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
; y; Z  d! m' N; |% p( u1499515 ADW            COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
1524947 SIG_INTEGRITY  SIGNOISE         SI Base, PCB SI: Custom Stimulus is not recognized correctly
1532162 CONCEPT_HDL    CORE             The Rename Signal command does not update split symbols.
0 s9 X/ l4 m) M- P1543997 CONSTRAINT_MGR OTHER            Import Logic is overwriting the constraints in attached design.
# p/ Y; d% d8 g0 s  m9 @4 Q- Q1544675 ALLEGRO_EDITOR OTHER            Export libraries corrupts symbols if paths do not include the current directory (.)
1549097 CONSTRAINT_MGR XNET_DIFFPAIR    Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
1 V. k5 H, [# b% w" q; O1551934 ALLEGRO_EDITOR SKILL            axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
* u; L* O9 F8 T1 e" R1 j1554919 ADW            LRM              LRM does not find PTF data for cell 'res' in the reference library
1555009 CONCEPT_HDL    INTERFACE_DESIGN Not possible to rename NG
1557542 ALLEGRO_EDITOR OTHER            DXF export creates strange result for donut-shaped polygon
7 l7 c* G7 ^$ ^5 q, U& k1 e1559136 ALLEGRO_EDITOR EDIT_ETCH        Cannot connect floating clines to vias with nets
- m$ Y/ r* D) O" j1560301 CONCEPT_HDL    CORE             DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
1560804 ALLEGRO_EDITOR OTHER            Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
+ g7 u& ?) P$ y, d1564036 CONCEPT_HDL    CORE             User-defined custom variables are not getting populated in the TOC
1564545 CONCEPT_HDL    OTHER            Signal model property deleted from an instance is not deleted from the instance pins
9 e1 b8 c( c. A& }' b1564552 CONCEPT_HDL    CORE             Find Net should zoom to the nets on schematic canvas
& W! N( ?+ H* E0 z. z1566119 CONCEPT_HDL    CORE             Right-clicking the schematic to add a component does not show all the schematic symbol versions
- A; R% w( G* i1 s1566848 ALLEGRO_EDITOR ARTWORK          Board Outline artwork is incomplete
) s6 f! p0 U- S1 w, D1567290 ALLEGRO_EDITOR MANUFACT         Import Artwork fails to import a shape.
" C7 B1 C" l& R1567587 ALLEGRO_EDITOR MANUFACT         Extended tool name in header of drill file is not correct
9 Y4 R# K6 G* ?! K  m% c' n( y1 i1569056 CONCEPT_HDL    CORE             Opening New Cascaded Window Causes Graphics Artifacts on Old Window
1569087 ALLEGRO_EDITOR DRC_CONSTR       Running DRC Update gives the message  'Figure outside of drawing extents. Cannot continue.'
1569147 CONCEPT_HDL    CORE             Signal Name AutoComplete Drop Down List Not Correctly Displayed
1569924 CONCEPT_HDL    CHECKPLUS        ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
, i* R7 Q) g- Y  p( [1570419 CONSTRAINT_MGR CONCEPT_HDL      How do I add a customized worksheet custom property weblink in Constraint Manager
: i# n  ]" k! T1570624 APD            ARTWORK          Artwork file has missing voids on a layer and is causing a short
1570678 F2B            DESIGNVARI       Variant Editor error when adding an RSTATE property
+ o) J1 h7 u& _1571113 CONSTRAINT_MGR DATABASE         Reports generated from cmDiffUtility show the differences in mm units only
/ r$ O4 K. M9 }5 S1572593 ALLEGRO_EDITOR ARTWORK          ARTWORK: 'Draw holes only' option does not match display
  k- q# X8 V. g7 p. M" @- V$ n7 C1573205 CONCEPT_HDL    CORE             dsreportgen is unable to resolve the physical net names (PHYSNET)
8 @: o& }2 S* u5 ]$ N: I1573970 CONCEPT_HDL    ARCHIVER         archcore fails to archive the <project CPM>.arch file
1574381 CONCEPT_HDL    OTHER            Packager crashes with some advanced settings
1576100 ALLEGRO_EDITOR SYMBOL           Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
1580103 ALLEGRO_EDITOR DATABASE         dbstat of 16.6 does not recognize 17.X files

DATE: 04-22-2016   HOTFIX VERSION: 069
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9 ?" }( X8 g2 N/ o6 O) `* yCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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2 a; b6 Y/ U1 I6 C6 d( w1272355 F2B            DESIGNVARI       Property changes on replaced component shows incorrect result in BOM output
3 z9 R* ]! G; s0 T1483136 ADW            COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
3 |5 e. d- l/ Q4 f/ q6 y- K5 ?1488909 ALLEGRO_EDITOR DRC_CONSTR       Test Via causes net scheduling verification to fail
1498389 SIP_LAYOUT     DIE_GENERATOR    Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
1506672 ALLEGRO_EDITOR INTERACTIV       Replicate Place - Shapes are missing
1523532 F2B            PACKAGERXL       Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
7 I+ d/ t" @6 z( m1 q. m8 g1525783 CONCEPT_HDL    CORE             \BASE scope does not work for SYNONYMed global signals
  S/ p0 X; m; d( P1 _1529846 ALLEGRO_EDITOR SHAPE            Some shapes are not generated in the artwork
+ ~: w/ \9 g) Y) f! L1537499 CONCEPT_HDL    CORE             Adding the same version (already placed) with the same split block name should not be allowed
: N8 k( R4 o% Q/ D7 ~1542334 CONCEPT_HDL    CREFER           creferhdl leaving lock files in sch_1 folder
1543410 ADW            LRM              LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
9 W: L. Z0 O0 O( _' M1546141 ALLEGRO_EDITOR SHAPE            Shapes missing from Artwork
8 m/ D7 \- j! F! P; M8 T0 S) B1546877 CONCEPT_HDL    CORE             Align Left on Wires Fails With Incorrect Error Message
1548953 CONCEPT_HDL    CORE             Genview generates a symbol with strange graphics - lines going to a single point
1548978 ALLEGRO_EDITOR MANUFACT         Shape not voiding clines
# {; ^* ]  u# z0 h2 e) P5 r  G1550941 PCB_LIBRARIAN  PTF_EDITOR       PDV Part Table Editor new column sorting causing problems
9 N/ X7 Y+ l: n1553950 ALLEGRO_EDITOR SKILL            Executing axlUIControl('pixel2UserUnits) crashes Allegro
1554333 CONCEPT_HDL    CORE             Changed connectivity error when aligning ports attached to netgroups
# p2 T8 }3 I$ F( l, f& ~0 u1555092 SIP_LAYOUT     DEGASSING        Degass offset is not working with hexagons
1556261 ALLEGRO_EDITOR DATABASE         Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
( t4 k; q# f, R0 w1557716 APD            OTHER            Stream out fails with request to terminate detected - Program aborted
7 e5 \; \5 m7 [% D1559951 SIP_LAYOUT     SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
: L: _6 b$ X0 K9 A1560197 CONCEPT_HDL    CORE             bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
1562537 ALLEGRO_EDITOR MENTOR           Mentor BS to Allegro 16.6 results in Fatal Error
. d, t6 D2 x0 w$ k; f1564203 ALLEGRO_EDITOR ARTWORK          ARTWORK : Can't generate negative film.

8 M8 R. h0 n( T2 iDATE: 03-23-2016   HOTFIX VERSION: 068
- u1 B! n$ H0 i0 z: m===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1522411 FLOWS          PROJMGR          License selection should persist on invoking Layout from Project Manager
% T7 k" }7 Z' m- N- e1544614 ALLEGRO_EDITOR SKILL            Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
1 S! [0 m- K) Q" ?1545909 ALLEGRO_EDITOR UI_FORMS         Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
  E0 B" U: ^0 `2 ~! L! M! i1546842 ALLEGRO_EDITOR OTHER            Unsupported characters: Not being reported by 'netrev' and causing nets to short
1547224 CONCEPT_HDL    CORE             Lock the 'PATH' property once it is assigned by system
1547584 SIP_LAYOUT     OTHER            SiP - Design Variant - delete embedded layer if not selected.
1548116 CONCEPT_HDL    CORE             Some versions of Technology Independent Library do not appear when adding a symbol
& T( {- C( P8 m) ^0 v1548151 ALLEGRO_EDITOR INTERFACES       Exporting a step file gives a component rotation mismatch in the *.stp file
  _7 E2 W, G0 \1548421 F2B            BOM              Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
1549105 APD            OTHER            'Stream out' fails with message: 'Request to terminate detected. Program aborted'
1549662 ALLEGRO_EDITOR OTHER            Import parameters fails if your parampath does not have .
1549836 CONCEPT_HDL    CORE             Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
6 O& V4 c3 a1 M8 d$ W4 f1550052 ALLEGRO_EDITOR PLACEMENT        PCB Editor crashes when copying symbols
7 c% s, `/ m9 S3 f" W7 I$ ^9 I4 w  i/ Y8 m
. S' z& j) N4 z8 J) h% @/ V. F4 HDATE: 03-11-2016   HOTFIX VERSION: 067
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5 X: P. \. @4 R5 s  h5 w$ M/ bCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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1482953 ALLEGRO_EDITOR DATABASE         Part change disassociates parts from Group
5 D; W' o: V4 d# a& j0 e4 Y1 K+ t1484075 ALLEGRO_EDITOR PADS_IN          'pads_in' imports ASSEMBLY_TOP  and PLACE_BOUND_TOP outlines that are defined as shapes as lines
1519155 ALLEGRO_EDITOR OTHER            IPC-2581-B Negative Plane Error
1528075 CONCEPT_HDL    OTHER            Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
/ m& T  h# O! s' G1528398 ALLEGRO_EDITOR SCHEM_FTB        Problem with pin number format used in NC property
1529178 SIG_EXPLORER   OTHER            Values not transferred correctly for PinPairs when created ECSET from a net
! I' J/ t# F7 e  Q: l0 |7 W* V* J1529720 CONCEPT_HDL    COPY_PROJECT     Running ADW copy project does not update the 'master.tag' file
7 \; a& ]+ c: l1530707 CONCEPT_HDL    CORE             Request to recover a 16.6 design after DE-HDL crashes
1532124 CONSTRAINT_MGR SCM              'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
$ U; C8 p/ D; B) N1532788 CONSTRAINT_MGR OTHER            Pin pair is hidden when Highlight Filter is ON in Constraint Manager
  U8 f, z( B" C6 J7 e9 W1536912 CONCEPT_HDL    CORE             Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
- K$ l2 F* W0 c. U7 c! d1537055 CONCEPT_HDL    CHECKPLUS        Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
; b& z% W) S' k/ w0 E6 t2 P1537278 SIG_EXPLORER   SIMULATION       SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
3 m" E! Z1 S  j& s( I- m1537339 CONCEPT_HDL    INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
3 d/ Q2 S) S: O8 M$ C* E1537521 FLOWS          PROJMGR          Do not allow project creation if there are spaces in directory or file names on the Linux platform
+ F3 ]9 q9 @9 H* _/ V1539227 CONCEPT_HDL    CORE             Renaming a page from the hierarchy browser crashes the schematic editor.
) u  ^' M7 F/ }: A9 x/ E1541532 SCM            SCHGEN           Generate Schematics crashes with 'Out of Memory' error
1541589 ALLEGRO_EDITOR INTERFACES       STEP model incorrectly shown in 3D viewer. Shows pins as angled.
1541680 CONCEPT_HDL    DOC              A dot (.) or period in design name created 2 separate design folders in worklib
1541687 ALLEGRO_EDITOR PADS_IN          PADS closed polygons are imported as lines
1542722 ALLEGRO_EDITOR INTERFACES       IDX export: RefDes and PART_NUMBER missing for mechanical symbols
; z+ I  P  y/ P. b. L1542817 ALLEGRO_EDITOR DATABASE         Import Netlist not getting completed on specific board
$ Q, I3 w  H( I. N1 N1544060 SCM            SCHGEN           Generate Schematics causes Allegro System Architect to crash
1544633 APD            STREAM_IF        The 'stream out' command causes Allegro Package Designer to crash
1544698 ALLEGRO_EDITOR PLACEMENT        'place replicate' does not add clines and vias to fanouts if fanouts are marked
1544859 APD            PARTITION        Timing vision menu is missing in APD/SIP partitions.
1545136 ALLEGRO_EDITOR PLACEMENT        All fanouts are marked as part of one symbol instead of the symbols they attached with
, T9 @" y6 Y1 \! g% w" Q1545370 APD            OTHER            Pads in .mdd file getting placed on different layers as compared to the design

DATE: 02-26-2016   HOTFIX VERSION: 066
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. j" V8 `& D7 J+ A# f1 PCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
* V& U% F' ^8 z% `===================================================================================================================================
5 ?) }, d4 R& J8 W2 O1523426 ALLEGRO_EDITOR DRC_CONSTR       Dynamic shape not adjusted based on keepout; DRC generated
1526729 SPIF           OTHER            Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
& u6 P1 b" t) t0 k  L9 W1529209 CONCEPT_HDL    CORE             When adding a component symbol version, the More option does not show all the versions
1530888 ALLEGRO_EDITOR INTERFACES       IPC2581 does not generate production files and fails with a segmentation fault message
) K% Z& U7 a( O3 k. P5 w* A3 ]# m1532865 CONCEPT_HDL    CHECKPLUS        Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
1536273 CONSTRAINT_MGR CONCEPT_HDL      Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
& w: F$ o0 v8 {/ u1538343 APD            OTHER            Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
1539077 ALLEGRO_EDITOR SYMBOL           PCB Editor crashes when choosing Layout > Renumber Pins
1539997 ALLEGRO_EDITOR SKILL            PCB Editor crashes when the axlStringRemoveSpaces() command is run
6 Q+ q3 Q8 W, g) `1541445 APD            DIE_EDITOR       There are two Recent Designs submenus in the APD Symbol Editor; one should be removed

: J- n  X6 P. a+ RDATE: 02-12-2016   HOTFIX VERSION: 065
# J$ a  l6 w) J3 n6 ]===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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% X* _0 d9 A2 ^& m! O5 w: [1511947 ADW            DSN_MIGRATION    Command line arguments of the 'designmigration' command are not working
+ h- _/ }5 L  r, c1517388 ALLEGRO_EDITOR SHAPE            DRC error reported as PCB Editor fails to read the void for a via
6 S6 ^& A# z2 W. j8 A7 b1521661 ALLEGRO_EDITOR PLACEMENT        'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
1522831 APD            OTHER            axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
* V3 Z! Z0 G8 V' x  ^0 B( _1524773 SIG_INTEGRITY  SIMULATION       Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
6 Q3 p# K# ?+ q2 J1524875 F2B            PACKAGERXL       Packaging using csnetlister fails, while manual packaging of individual blocks works fine
1527785 SIP_LAYOUT     WIREBOND         SiP Layout stops responding when adding a wire to an existing finger
5 P; I6 j2 s- X# ]9 @: t) y: L* D1528479 ADW            LRM              LRM crashes when opened on a lower-level block in a hierarchical design
1531425 CONCEPT_HDL    CORE             DE-HDL crashing while trying to add a NetGroup
1532722 ALLEGRO_EDITOR NC               Backdrill NCDrill files not getting created with PA3100 license.

DATE: 01-29-2016   HOTFIX VERSION: 064
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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# m' S( V, U6 [1510387 FSP            EXTERNAL_PORTS   Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
1514132 ALLEGRO_EDITOR INTERFACES       Element position changes after importing DXF
1514285 ALLEGRO_EDITOR TECHFILE         Importing .tcf file from Constraint Manager does not import user-defined properties.
1515580 ALLEGRO_EDITOR EDIT_ETCH        Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
: }0 J3 Q7 m, R1519040 ALLEGRO_EDITOR DATABASE         Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
1519910 CONCEPT_HDL    INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
- Z& U+ w. \% Z7 G- |, F1519943 ALLEGRO_EDITOR DATABASE         When user units are changed from 4 to 2, the design seems to disappear from the canvas
1519946 CONCEPT_HDL    CORE             Renaming a net leads to loss of constraints associated with the net
1519987 ALLEGRO_EDITOR SCHEM_FTB        In Hotfix 61, constraints are lost on importing a netlist
4 ^. d! C$ S( _# R9 S1520727 CONCEPT_HDL    CORE             In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
7 K# ?% m' m/ C( J1521174 SIP_LAYOUT     DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
1522227 SIP_LAYOUT     IC_IO_EDITING    SiP Layout stops responding when trying to add a co-design die (.xda file)
1522900 ORBITIO        ALLEGRO_SIP_IF   Padstack shape distortion after translation to OrbitIO from SiP design
1523237 ALLEGRO_EDITOR SKILL            SKILL function axlDBGetExtents() causing PCB Editor to crash
1524641 ALLEGRO_EDITOR DATABASE         PCB Editor stops responding when updating outdated dynamic shapes
+ v- B5 t- \5 ]+ ]1 G% h( z1525432 CONSTRAINT_MGR OTHER            User-defined property not being transferred from DE-HDL to PCB Editor
! x. G1 P% `2 _, Q6 U; o1525948 F2B            PACKAGERXL       Reference designators assigned by the Packager tool are not correct
1527321 ALLEGRO_EDITOR SCHEM_FTB        Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
# i4 D8 S' n0 a8 Y3 r, t1528254 CONSTRAINT_MGR CONCEPT_HDL      Import Logic with the 'Overwrite current constraints' option is deleting some attributes
% G" H& o0 b% i: l' ]6 k) V2 m
DATE: 01-15-2016   HOTFIX VERSION: 063
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
2 U; T- z8 ]0 c) Z5 t! i===================================================================================================================================
1472414 ALLEGRO_EDITOR SCHEM_FTB        netrev changes pin-shape spacing rule in constraint region
1494194 CONCEPT_HDL    CORE             Random display of the 'PHYS_NET_NAME' property in hierarchical designs
1500190 ALLEGRO_EDITOR EDIT_ETCH        Snake Router Creates Line-to-Line DRCs
4 p! }9 a7 P9 D) u( i! U1501093 SIP_LAYOUT     OTHER            Package design variant shows wirebonds connected to a die which is not part of the variant
1509184 ALLEGRO_EDITOR DATABASE         BB vias in mirror have terminal pads suppressed by artwork
1511397 SIP_LAYOUT     TECHFILE         Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
1511744 ALLEGRO_EDITOR OTHER            Allegro PCB Editor removes property from component instance
1511761 SIG_INTEGRITY  OTHER            Allegro PCB Editor crashes on running the cns_show command.
3 Q3 K! v8 g/ @  @* g! c1511787 ALLEGRO_EDITOR INTERFACES       IPC-2581 not exporting overlapping shapes correctly.
" |2 v, c0 V6 r6 K+ V" N1512071 ALLEGRO_EDITOR OTHER            The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out
2 p0 }" z, [3 b* Z( o, t1513085 CONCEPT_HDL    CORE             NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
1514469 CONCEPT_HDL    CORE             Unable to get rid of an underscore from the PHYS_NET_NAME property
- H; N3 J! @: }6 D1515318 PCB_LIBRARIAN  IMPORT_EXPORT    Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
7 c+ i* a' c/ G  O  c3 P1516093 ALLEGRO_EDITOR PADS_IN          Pads library translator does not translate slot orientation
9 r7 M; l& J  }9 p* u1517351 CONCEPT_HDL    CORE             Genview does not update an existing split symbol
8 D" R5 h# y, u( r1518032 CONCEPT_HDL    SECTION          How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
1518724 PCB_LIBRARIAN  PTF_EDITOR       PTF Editor is not saving changes
8 D$ c2 b, C& P& y- Z, q1519518 CONCEPT_HDL    OTHER            Genview does not generate split symbols
1519623 CONCEPT_HDL    CORE             Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
9 _' S5 W2 L+ v1 E$ Z+ l1520207 CONCEPT_HDL    CORE             Genview crashes after renaming ports
+ o7 p; q' g; a+ k6 Z7 ?; Z
8 j4 F  V! g" H1 QDATE: 12-11-2015   HOTFIX VERSION: 062
$ W3 j2 B- G* l- v. W===================================================================================================================================
5 P1 u0 q$ r/ u" z% FCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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2 B! ?% \4 {0 d& X1012606 ALLEGRO_EDITOR REPORTS          Natural sort option for Report output
$ B6 M) f  z3 g% m$ M1408218 ALLEGRO_EDITOR MANUFACT         Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
7 Y) g9 Y7 d( q6 C0 F1440509 ALLEGRO_EDITOR PLOTTING         Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
- s) q' s. z: o, V/ m! U0 w+ w- A1444144 ALLEGRO_EDITOR DRC_CONSTR       The 'add taper' command generates line to line spacing DRC
* H& [" i% I8 ?, R7 t" `) ?& Y& I1471275 SCM            UI               Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
1474764 ALLEGRO_EDITOR PLACEMENT        In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
1474894 ALLEGRO_EDITOR PLACEMENT        Place replicate fails to include vias when the module is applied to other circuits.
1485931 ALLEGRO_EDITOR INTERFACES       Errors generated when importing IDF in an existing board file
* G; p) N5 B7 T1 t0 y1487603 SIP_LAYOUT     WIREBOND         SiP Layout XL - Add multibondwire option to non-standard wirebonding
1490311 SCM            OTHER            Block Packaging reports duplication when it should not
0 c( Z4 }3 j% j; b( V3 U. {1491272 ALLEGRO_EDITOR EXTRACT          Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
1491521 F2B            PACKAGERXL       Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
1492013 CONCEPT_HDL    CORE             Stale PNN properties not cleared from schematic on packaging design (backannotation)
1492703 CONCEPT_HDL    OTHER            'Global Property Display' not working for symbol edit
2 ?) k" B" f9 S; O1495296 SIG_EXPLORER   OTHER            The T-point sequence in SigXplorer is different from the layout
" M, y4 c) W0 k) V" u! i. n1495789 ALLEGRO_MFG_OP CORE             DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
; u/ J& j7 l* _! K- I1496286 ALLEGRO_EDITOR PLOTTING         Export PDF is not exporting hidden, phantom, and dotted line types
1499051 ALLEGRO_EDITOR PLOTTING         PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
& X" K/ ~8 J, [$ L- a( F1499380 SIP_LAYOUT     DEGASSING        Oblong shape degassing voids are not created correctly
1499538 ALLEGRO_EDITOR PAD_EDITOR       Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
" Q4 g+ k- ?8 x1500422 ALLEGRO_EDITOR SKILL            SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
% o8 C0 M+ l% z4 s1 w7 K9 R1500659 FLOWS          PROJMGR          Need the ability to ensure that the standard library is not added to the project libraries list by default
1500725 F2B            PACKAGERXL       Unable to clear pstprop.dat file conflicts
$ y; L" Y; M/ Y% l8 z& C1501139 ALLEGRO_EDITOR PADS_IN          Pads_in creates pastemask for Through Hole padstacks
1501165 F2B            DESIGNVARI       TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
# N' x9 D% g2 j1 K, x1501774 ALLEGRO_EDITOR OTHER            PDF Publisher: If text is attached to an object, the object is also printed in the PDF
1501898 F2B            DESIGNVARI       Variant custom variables are visible in the schematic border but are not there in the Variant Details form
1 p6 n- Y8 h1 q/ Z1501974 F2B            PACKAGERXL       'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
3 O7 `5 N7 q0 f; L, v" ^7 [4 d1502782 ALLEGRO_EDITOR SCHEM_FTB        Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
1503551 APD            STREAM_IF        In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
0 H. p3 x! j- y" e( L/ O# \1504093 ASI_SI         GUI              View Topology and Waveform buttons overlap when Signal Analysis window is resized
* q' D5 [9 h7 o1504767 CONSTRAINT_MGR SCHEM_FTB        Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
1505497 SIP_LAYOUT     LOGIC            Assign net fails to fully connect propagated items
1506110 ALLEGRO_EDITOR DRC_CONSTR       No DRC shown when a text on etch layer is overlapped on mechanical pin
1506654 CONCEPT_HDL    INTERFACE_DESIGN Netgroups broken when moving
1506983 ALLEGRO_EDITOR SKILL            axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
; d, g: S3 ?) S) X
DATE: 11-20-2015   HOTFIX VERSION: 061
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
; J$ P* U8 [: g===================================================================================================================================
1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value
1342644 ADW            COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
1413248 CONCEPT_HDL    CORE             Import from another TDO project makes the block read-only
3 M1 R7 Z* L! o2 i9 ~1417429 ALLEGRO_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
' v1 U9 X/ S+ x$ M7 V  a1 V1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins
6 G9 J0 g: G, y& g1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
1453527 ALLEGRO_EDITOR EDIT_ETCH        Contour route hugs the outer edge of the route keepin
3 z4 A7 B) {! s! \' l! u/ w; k9 @6 U1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools
1467826 CONCEPT_HDL    PDF              PublishPDF from Console Window creates a long PDF filename
1478639 CAPTURE        OTHER            Capture Browse Nets window does not display all nets
0 b3 w& U0 [% Z% P7 i% P5 Z1479177 SIP_LAYOUT     OTHER            Pin pair constraints do not appear to be supported in Sip Layout XL
$ i/ v6 `. N0 Q4 m) a# m3 F1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable
9 y- s1 g) o$ |) q2 @1480293 CAPTURE        PROJECT_MANAGER  Capture hangs when searching for all nets
1483894 CONCEPT_HDL    CORE             Import Design hangs when pull-down arrow is clicked twice
  Q' ~4 f$ J% _4 p7 W1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues
1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only
1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project
  n. \- h3 w1 G; J5 O; K/ f1 j# T1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.
; l' p  U1 C# M* c7 m: S2 ^1486834 CONSTRAINT_MGR OTHER            Restore the Status column in cmDiffUtility
4 u8 B' D% }, n' ]6 H0 b, F! _7 ^1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems
1487197 ALLEGRO_EDITOR DRC_CONSTR       Drill to Via DRCs are not being reported
8 i4 S: t8 U' L8 }7 O2 T( q+ M1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior
- M: h/ H. d' R) A& o5 \( `" V1487733 CONSTRAINT_MGR OTHER            Running Export Physical - It takes over two hours to update the PCB Editor board
1 N/ B5 ^7 K1 T% A+ p1488758 CONCEPT_HDL    CONSTRAINT_MGR   CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
1490299 SCM            OTHER            ASA does not update revision properly
7 |) |- y( U* I: ]- O7 n3 P1490744 ALLEGRO_EDITOR SKILL            axlChangeLine2Cline changes line to cline and places it on the TOP layer
1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints
3 @; H) Z( ]" L3 ?; V7 g1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working
5 h& I9 Z3 I& A6 Z( Y1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong
1 W+ T! ?( V; U9 Q% Y1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO import of customer mcm results in crash
1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
1495621 ALLEGRO_EDITOR INTERFACES       Oval pins are placed with wrong orientation in IPC2581
1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size
1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
' N& Q; ]# H2 j6 B  U2 m1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file
1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix60

jacklee_47pn

截至目前 071 版本，
有關 CAPTURE 最後補丁到 061 版。
. X1 S! U) X; T5 c4 Y: I有關 PSPICE  最後補丁到 058 版。
4 f0 x6 z1 I% [- Z只用上面所說的二項軟件的朋友，不用追補丁到處跑。

hermes

何处下载？

jacklee_47pn

hermes 发表于 2016-8-17 13:05
. ]. v+ L7 p/ G# L, N' f; l% i何处下载？

) U# A$ Z$ z" n) N" E+ nHotfix_SPB16.60.073_wint_1of1补丁

http://pan.baidu.com/s/1i5jStCx

hermes

已下载，谢谢!

jacklee_47pn

新增  076-072 版的補丁內容

2 r7 g4 G/ O1 w$ S/ S
, D' R. i( Y2 J8 |DATE: 08-25-2016   HOTFIX VERSION: 076
===================================================================================================================================
8 D3 ~3 ]& m- Z4 ~CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
" |, }9 d, w8 g& P) U7 I===================================================================================================================================
1614667 SIG_INTEGRITY  SIMULATION       Different results from Probe in SI Base and SigXp
  x5 P, z# z1 c1615601 GRE            IFP_INTERACTIVE  Delete Bundle then try to delete plan lines results in fatal error
1616540 SIP_LAYOUT     DRC_CONSTRAINTS  Same net DRC Line-to-Line reappearing after dyn shape update

1 z3 {' l4 Q8 Q, P: G; x, VDATE: 08-12-2016   HOTFIX VERSION: 075
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1461626 CONCEPT_HDL    CREFER           Cross-references shown to the same pin on different block instances though the signal names differ
4 c  k' X2 E3 K5 H4 O9 T2 f, \% l3 |1597000 CONCEPT_HDL    INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names
1602801 SIG_INTEGRITY  OTHER            Dielectric Warning message when opening SiP tool.
1606861 CONCEPT_HDL    CORE             Crash on Linux during Generate View
1608524 SIP_LAYOUT     MANUFACTURING    The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
1609922 CONCEPT_HDL    INFRA            Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only
1612108 ALLEGRO_EDITOR OTHER            Netlist Import is crashing with the .SAV message.

DATE: 07-22-2016   HOTFIX VERSION: 074
2 q& e: j' I. O# r===================================================================================================================================
4 W$ d5 e5 \) \! UCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
7 c. m' o, }- O  _) h===================================================================================================================================
( ~! E' `" S. \0 y0 L/ A9 [6 K& o1423889 ALLEGRO_EDITOR EDIT_ETCH        AiDT gets poor routing result
0 v  H7 ], n2 b$ w1547356 ALLEGRO_EDITOR EDIT_ETCH        Results variations from ISR S034 to S066
1568912 RF_PCB         BE_IFF_IMPORT    Route keepouts can only be imported once
1574676 ORBITIO        ALLEGRO_SIP_IF   sip->oio eco doesn't work properly
1580744 F2B            PACKAGERXL       ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
. s! @0 A) ?9 d' I$ r9 `1 ]1 W0 r1582628 ADW            TDA              When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
1584719 TDA            CORE             Caching errors coming for a board ref project while doing Block update
1587157 CONCEPT_HDL    CONSTRAINT_MGR   pstprop.net reports conflicts on nets with VOLTAGE properties
1587498 CONCEPT_HDL    INTERFACE_DESIGN Possibility to tap bus bits removed
, w! Q3 A* [( i% y& A1588786 ALLEGRO_EDITOR OTHER            strip_design reports "Design corrupted message"
1589252 CONCEPT_HDL    CORE             Search options go to page origo not chosen component
* M; x2 J7 o: c4 ~1590538 CONCEPT_HDL    DOC              Open Archive shows unclear behavior
1590639 CONCEPT_HDL    OTHER            DEHDL crash when importing design
0 y3 }1 _) d% |1 V7 _+ W' X+ f! F1590651 CONCEPT_HDL    INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM
1594076 TDA            CORE             TDO is crashing on concurrent checkin when one of the user got blocks which are not modified
9 W8 K! T# q& J( D; Y1594358 CONSTRAINT_MGR CONCEPT_HDL      Enable hierarchical BOM fails for sub block with working variant view
1596780 ALLEGRO_EDITOR SKILL            PCB Editor crashes after doing SRM update and save
) X( ]) Y. i# I) m) x: r/ y1597153 F2B            DESIGNVARI       ERROR SPCODD-53 in Variant Editor
1597385 F2B            DESIGNVARI       Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
5 Y% n$ b# A& E, b1597413 SIG_EXPLORER   SIMULATION       SigXp crashes when simulating with via that was added to canvas
1598629 F2B            PACKAGERXL       Export Physical crashes
1599452 ALLEGRO_EDITOR ARTWORK          Import Artwork, Mirror option does import pins or shapes.
! f8 s  {0 t6 ?4 P2 ~4 }* d3 \1599950 SCM            OTHER            Adding the GND net to parts/pins takes a long time.
2 ^/ r5 N; n3 b. j' G1600226 RF_PCB         AUTO_PLACE       Fail to auto-place RF group
( {& \- W+ E* @* W0 [" j1601281 ALLEGRO_EDITOR OTHER            STEP model link gets corrupted with SKILL axlLoadSymbol
6 p0 u1 ^  N$ O% V, V3 Y8 ~1601282 ALLEGRO_EDITOR OTHER            Export Libraries will not export device files when there is a space in the folder name.
2 \) y5 J" W- j+ p1602186 PCB_LIBRARIAN  VERIFICATION     con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses
3 r% W) H/ ^) {( X4 {) m1602514 PCB_LIBRARIAN  METADATA         References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
7 H, N/ z0 m0 r* h2 ]* N/ S3 p1602823 SIP_LAYOUT     WIREBOND         SiP Crashed during Add Wire command
1602955 ALLEGRO_EDITOR SHAPE            Shape no DRC when there is a Route Keepout in base layer.
; \- l. Y* N7 Z6 n  X% x1 ~6 e( l1604223 CONCEPT_HDL    CORE             ERROR: SPCOCD-553: Connectivity Server Error
1605310 TDA            CORE             TDA is crashing sometimes in the Join Project wizard
* W# \. ~* e% }
DATE: 06-24-2016   HOTFIX VERSION: 073
===================================================================================================================================
9 S+ t5 P2 y% p* `" Q0 tCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1570032 ALLEGRO_EDITOR GRAPHICS         Issue with 3D View
0 P; U2 {! c) H! @: h" a1582103 ALLEGRO_EDITOR PADS_IN          PADS Library Import creates additional filled shape not present in source data
1590954 ORBITIO        ALLEGRO_SIP_IF   import of brd file fails with "Undefined argument" error
1591223 CONCEPT_HDL    CORE             Variant information does not display on lower level schematic

7 I1 H  Z# o; ADATE: 06-3-2016    HOTFIX VERSION: 072
2 v9 Z) w/ l$ l. _- q. b: j===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
" c, O5 S% L1 L0 L" \/ S===================================================================================================================================
1546151 CONCEPT_HDL    CORE             Add port, Genview, move pin on block - the pin name disappears
( @9 @# ^& q  f2 x. d  e2 [1566274 RF_PCB         FE_IFF_IMPORT    RF-PCB -> Import IFF crashes in DE-HDL
1573039 ALLEGRO_EDITOR INTERFACES       IDX returns control to the general interface prematurely during an incremental IDX export
1573127 CONCEPT_HDL    COPY_PROJECT     copyproject creates incorrect view_pcb entry
1577381 CONCEPT_HDL    CORE             ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure
4 I+ J* [' y  e4 M1580891 SCM            REPORTS          Dsreportgen crashes on different scenarios
1582863 CONCEPT_HDL    CORE             Generate View creates non existent ports
2 Q' Q! n0 n: q& X, _( L1584317 CONCEPT_HDL    CORE             When  packager fails, no option to open pxl.log file from design sync window.