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本帖最后由 partime 于 2016-8-10 20:06 编辑
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不知道有没有人上传分享,我刚下载上传过来,现分享!
, f# o8 x# U j0 G& M链接在下面,回复可见。顶起来,让更多的人看到!还有CCR,可以看看都修复了什么内容。% b9 ~1 Z2 W) M$ q
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5 }9 C- n& d1 [# ? { q5 f1 mCCRID PRODUCT PRODUCTLEVEL2 TITLE1 v( M# N6 E6 t1 M/ v
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1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result
) i( k$ k. r* n2 A 1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066
- N3 }. D5 V% a- _0 M 1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
! e) O' m$ C+ k& c 1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
2 ^# @/ Y( }% Y+ F# F& J$ P) m( [ 1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found/ \6 p; N& U1 p0 N" G- G7 R* n
1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
. O/ n) V% z9 F- {- j5 g8 d& y 1584719 TDA CORE Caching errors coming for a board ref project while doing Block update8 I3 k- Z# O \9 |
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties
b3 x+ `( B, ?6 @- X5 f8 v 1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed
5 L0 \$ D6 q2 p% g 1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
" y8 w4 f4 l; [7 V: c. Q 1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component
, _; i5 n" c/ n/ f! y 1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior
6 Q7 P' F6 U5 u& M1 ^3 F' Z 1590639 CONCEPT_HDL OTHER DEHDL crash when importing design
1 _, [, s3 s8 I1 R 1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM* G' w& B3 x a$ F" }6 A, T& [
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified/ x3 O- p: s7 K
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view
L6 T" e8 v) q, S# ^; h3 m0 \ 1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
, j0 }2 G4 q& F 1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
: D0 q" a/ E/ D, p/ y" ]+ | 1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
9 s' t1 L& t5 O8 H( p9 w w" T7 a 1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas3 O% L; r! b7 E9 B/ Z5 A' S3 [
1598629 F2B PACKAGERXL Export Physical crashes" t( |) J* N6 m+ k
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
4 q) g+ w5 x6 v8 s* c6 e6 q+ }( A 1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
: D8 P+ H. v) E& h7 w 1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group
' M; U* _: o1 P: H1 \ 1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
# j7 t2 g3 d; @, ~) s A+ m6 \ 1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.4 b* V1 _4 u& x
1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses
& g1 F4 c3 |3 V/ \0 S/ V6 z% v 1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
) A+ G" z6 s: C8 c 1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command$ v% W& K) e7 x4 A: V
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.
! f& K6 Y1 P( ]9 ^6 L% b 1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error+ D3 d# D9 x: S, [7 W0 x2 K
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard/ I5 k& P7 B& D$ g2 b8 J/ o
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