这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？
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- s% G$ d( Q+ X. o2 t3 z1 [" {If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
( X4 O9 R) f3 \/ nassertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
& J( a& O$ ^% X: m& d2 C) fissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
% U' d) w# O, @8 k* L  sAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
- c% b: G; k# Gdue to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
4 B# m/ B7 n0 G. l% Q6 N5 Qreset glitches. If this is a real problem in a system, then one might think that using synchronous
: p3 j/ M% B3 i3 v$ mresets is the solution. A different but similar problem exists for synchronous resets if these
spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
true of any data input that violates setup requirements).