|
换了nandflash后和加焊DDR后有两种状态,但是板子都没有启动成功,串口有打印。
5 C/ `) n, Q2 d: p; @$ M# o! |以下是状态1的log:- X, {4 f# h+ I& M( @1 L
SoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)/ \$ T3 ]4 b. g9 u: T
II: Stack @ 0x9fc1fd18 (parameter 736B)
9 h6 O* z: J9 gII: Console... OK! V( L: p) K5 O9 ~! s
Setting DTR0 g: c3 T6 Y& s# h
II: DRAM is set by software calibration... PASSED
+ u$ y: x& `7 T: D/ G2 \/ a" x6 i* j! Z) p( J
DDRKODL(0xb800021c):0x00000410
H& V& U0 F9 @MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f
; r2 E1 k6 M J7 z" rDTR2(0xb8001010):0x0630d000
/ J! J S8 K$ _$ h5 h, v: o* q0 rPHY Registers(0xb8001500):
: b6 h8 F, X6 C& P0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xfdffffff
8 M1 q* L( h4 ]9 }+ c+ s0xb8001510:0x00140a00, 0x00180c00, 0x00140a00, 0x00180c00
( q$ ?/ e- [ B. s1 I0xb8001520:0x001a0d00, 0x00140a00, 0x00160b00, 0x001209002 S7 I& W1 a" b8 z( {( M- t
0xb8001530:0x001c0e00, 0x001e0f00, 0x001c0e00, 0x001e0f00
$ [! {. c: q6 N0xb8001540:0x001e0f00, 0x001a0d00, 0x001c0e00, 0x001a0d00% {# I2 Z" u, ~ Y
0xb8001550:0x00100800, 0x00140a00, 0x00100800, 0x00140a00
5 k+ j- ^2 @5 \$ `0xb8001560:0x00160b00, 0x00120900, 0x00140a00, 0x00100800: v' S7 P( f2 f; a% q& N0 m, h# G# i
0xb8001570:0x001a0d00, 0x001a0d00, 0x00180c00, 0x001c0e00- F2 ?: I0 @+ }) r4 p0 q, A! i4 U8 x
0xb8001580:0x001c0e00, 0x00180c00, 0x001a0d00, 0x00180c00
8 M& E& g1 V2 W- ?/ x+ t0xb8001590:0x00000000, 0x5110dbd9, 0xa9a95656, 0x5352b5b54 u1 j0 {# V1 N- t/ @; V; b7 b
0xb80015a0:0x4145dcdc, 0x00000000, 0x00000000, 0x00000000
, D2 p. ^: I9 PII: PLL is set by SW... OK/ z0 g* [1 ^5 U9 E# ^* `
II: Flash... OK5 u* L G: q8 I' k
II: Stack @ 0x801ffff8
8 P1 N: S/ Z9 o# y' C+ QII: Starting U-Boot...
1 ^. {5 g2 c$ V; h" P+ A6 p5 [II: Inflating U-Boot (0x80000040 -> 0x87c00000)...
5 D3 S- v/ l( o: S$ S; tEE: decompress failed: 19 @6 `4 P7 ^( p6 E' B. ]5 p
以下是状态2板了log:6 ~4 S* w4 `- I. Q9 |7 Y, X& x6 N2 L
SoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)" ]+ p2 w- ~3 M+ c" d! {
II: Stack @ 0x9fc1fd18 (parameter 736B)
- I4 i3 `6 L0 k& O2 T2 g9 hII: Console... OK
2 N, k+ S- \7 }2 T1 cSetting DTR! [& p- ]" |& t) _9 Q/ h) b) e/ p! ]
II: DRAM is set by software calibration... PASSED$ T& R- U0 u; t ?: P
' Q9 ]; J$ b6 S' }! x
DDRKODL(0xb800021c):0x00000410
2 R# w7 P. b% s Q- T' {MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f' h" V: V0 e" i9 _* i. ?5 Z
DTR2(0xb8001010):0x0630d000
; ^$ A* n4 p0 g$ yPHY Registers(0xb8001500):
& f, Y# | C/ f0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xffffffff
' H& y" v0 r9 y- |0xb8001510:0x00120900, 0x00140a00, 0x00120900, 0x00160b00) \9 c( J* b' _3 }& p9 l) f
0xb8001520:0x00140a00, 0x00120900, 0x00140a00, 0x00100800
. G/ g" `, K/ ^- B6 _: }7 E0xb8001530:0x00180c00, 0x001a0d00, 0x00180c00, 0x001a0d00
; O" @9 {2 D; a% J5 S# B: p+ N0xb8001540:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c009 L# ]2 j; D- h( }
0xb8001550:0x00120900, 0x00160b00, 0x00120900, 0x00140a00
& H9 `7 R% |( z/ i0 P" _0 c) `0xb8001560:0x00140a00, 0x00140a00, 0x00120900, 0x00100800 T$ {2 u" m- i! x0 T) \
0xb8001570:0x001c0e00, 0x001c0e00, 0x00180c00, 0x001c0e005 X( G* D5 d' w9 {" c5 G3 k# A
0xb8001580:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c00/ H& \6 z6 ?6 `1 s) e3 J
0xb8001590:0x00000000, 0x5adad2d2, 0x24207574, 0x5a5adada
/ S# ~! G X7 V' @0xb80015a0:0x8d0da7a5, 0x00000000, 0x00000000, 0x00000000
) x, e$ J( O! R6 `% i* _4 xII: PLL is set by SW... OK
% M( P g, ?2 n) w9 c: x3 m0 ^II: Flash... OK. q N' _+ |& H; Y: k
II: Stack @ 0x801ffff8
$ W) U; \' Z3 Z2 Q2 M9 LII: Starting U-Boot...7 I& q$ ?: }$ H: ~
II: Inflating U-Boot (0x80000040 -> 0x87c00000)... OK
* D9 [7 D `: u- S9 c. A/ v( UII: Starting U-Boot... 6 v2 k2 u3 {4 K" {
7 z3 c1 A0 B; `: K
! U; a; d; M M2 n, ^ r2 BU-Boot 2011.12.NA (Nov 13 2013 - 14:33:03)
6 J6 ^7 ?& O9 ]! L% J# [; l/ {' w; P0 l' Z+ L- P1 b9 {
Board: LUNA
% o; v. b. x4 W+ c* ^CPU: RLX5281 600.00 MHz, DSP: RLX5181 500.00 MHz, , DDR3 300MHz, LX:200.00 MHz
& w {6 p4 X1 U% GDRAM: 128 MB0 w& ~; T) N$ Y6 Z0 T c
enter nand_init
* _7 p7 K, s/ Mboard_nand_init()
& t) @0 Z7 Q F; V3 A) Y5 O5 Eparameters at 0x000012128 ^! E7 L5 W1 q$ g/ N& S6 J
parameters.read at 0x9fc00550
: r+ \- p" z3 L @parameters.write at 0x9fc033082 t& `3 o3 C/ M( N( ]. m# F
parameters.bbt at 0x9fc1feac
8 ]9 ?- I7 O& Auboot- read nand flash info from SRAM
9 a9 q) Z) X& o8 @flash_info list: @" m6 d1 T/ S
flash_info.num_block : 1024
% E! }' m: {) Z1 V$ xflash_info.num_page_per_block : 64
$ } i5 A! L, G2 s# B1 t1 [$ zflash_info.page_per_chunk : 1
1 m( [ Q7 f. Y! |4 u& Sflash_info.bbi_dma_offset : 2000
; Y* X- q2 F1 E) z0 b: `flash_info.bbi_raw_offset : 2048% E* [: {, p7 X$ i$ Q1 g
flash_info.bbi_swap_offset : 23
1 O* E8 F7 t* M+ y' S( Yflash_info.page_size : 2048) `% G7 k0 Y% ? G( g. C
chunk size : 2048
. I7 c# V1 p7 Q# n1 V) O+ vflash_info.addr_cycles : 41 e5 n; n6 j+ |) q$ n
pblr_start_block : 1
, l+ i2 ]2 ~/ w/ U5 ^) g6 knum_pblr_block : 3
" v4 `, o8 p1 _- Mparameters.curr_ver is a0 k6 p* X7 p) P5 n% T& \" V3 a
parameters.plr_num_chunk is 29, w! M, v- E/ H
parameters.blr_num_chunk is 45; ^% x! z" K& P' s
parameters.end_pblr_block is 4. p9 ?4 p( R& m% q* D
rtk_nand_read_id id_chain is 9580f192
$ v1 A6 H5 h: h) V) qnand: Manufacture ID=0x92, Chip ID=0xf1, 3thID=0x80, 4thID=0x95, 5thID=0x40, 6thID=0xc0
* ~9 D/ A! U, n8 _0 _3 othis->pagemask is 65535
5 H n) s" c$ y' f, Ythis->chip_shift is 27( M# T/ {- [- a3 w9 k0 I+ U9 \7 s
parameters.bbt_valid is 1
9 L) h, ^5 k( _: {2 O' u7 A6 Gcreate_logical_skip_bbt- t' }: i4 `+ p: ]4 j
last skip_block 1024
2 w. ^/ c1 r8 m5 h5 M( _$ C. [nand.c nand_init_chip mtd size is 877bfeac) ^. g4 N' ^" Z- E0 I0 M
128 MiB! g. v& j) Y4 W
Loading 131072B env. variables from offset 0xc0000
) ]1 \( n7 T, S& UUnknown command 'sf' - try 'help'0 H& D& L( |3 L9 [% n
Net: LUNA GMAC
8 o- a4 X( r, \1 u: ~$ P! r% rWarning: eth device name has a space!) K. x+ t. d2 e
9 R. P. Q4 c/ G0 A
Hit space key to stop autoboot: 0
: L% R. `2 H6 i' G' m, z- K8 F1 Q1 N2 E$ ?1 D2 ~! K- E
- a- H: y, F& R* G7 _3 I9 X. \
ACTIVE IMAGE 0 (tryactive=2 sw_commit=0)4 A0 E9 [+ C5 L% t
1 r# d# Y+ m; w* W3 Ereset pcie0
( [ R& }- N1 L4 p# W' A- e ?/ jreset pcie19 y0 ^0 t7 Z/ t1 Q6 r
4 M4 Y! w$ f8 c4 V5 x( v* }/ B7 x4 LNAND read: device 0 offset 0x100000, size 0x380000
! j2 l7 g2 D1 `2 y* @ 3670016 bytes read: OK
$ k1 [3 d# ?" ^/ Y; [## Booting kernel from Legacy Image at 82000000 ...2 ?- E& M- V. v& S) u
Image Name: Linux-2.6.30
. z* O. |1 \' X3 X Created: 2013-11-14 2:56:37 UTC6 x& h. y$ f7 V/ ~( I
Image Type: MIPS Linux Kernel Image (lzma compressed)8 Q& F& F. A1 [8 H }1 {7 B. e
Data Size: 1791872 Bytes = 1.7 MB5 }# }- p, v8 l5 W' P
Load Address: 80000000
6 Q* l0 f. s$ K, j5 G9 Z! S" i- x Entry Point: 80000000
* c# Y$ ~/ B: [% O0 |- ~ Verifying Checksum ... Bad Data CRC
+ q- t* }" B8 j9 d8 \* CERROR: can't get kernel image!, w5 l& n0 y" o$ n _" _: g: m
5VT-2510# 9 |" W, c1 p: v1 X5 b, \3 t8 c2 c
请问大家这是什么问题呢? |
|