DDR4离我们还有多远

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转自JEDEC
# }! V2 k4 O9 v8 O$ G3 C. S8 k9 bMain Memory: DDR3 & DDR4 SDRAM
! o* P' b$ n- x5 O- `/ vSemiconductor memory plays an essential role in the development of countless electronic devices ranging from computers and gaming consoles to televisions and telecommunications products. JEDEC standards encompass virtually every key standard for semiconductor memory in the market today.
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JEDEC DDR3
5 z9 S, F) k) p$ d5 v4 P$ |& @$ d: GThe JEDEC DDR3 SDRAM standard describes an evolutionary memory device offering improved performance, lower power and greater functionality than earlier generation memory devices (e.g. DDR1 and DDR2). The JEDEC DDR3 publication defines specification details that enable manufacturers to produce memory devices offering double the performance and density as previous generation (DDR2) devices, with reduced power consumption. In addition, it is envisioned that the DDR3 specification will be extendable to even higher performance and lower power consumption.
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In July 2010, JEDEC published the DDR3L low voltage memory standard as an addendum to the DDR3 SDRAM standard, which may be found here: Addendum No. 1 to JESD79-3.

JEDEC DDR4
With publication forecasted for mid-2012, JEDEC DDR4 will represent a significant advancement in performance with reduced power usage as compared to previous generation technologies. When published, the new standard will be available for free download at www.jedec.org.

DDR4 is being developed with a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard.

6 t2 ]6 g7 [3 y3 Q5 d9 e4 CA DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. Understanding that enhancements in technology will occur over time, DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable.
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The per-pin data rates, over time, will be 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its expected peak of 1.6 GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future. Other performance features planned for inclusion in the standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667 Mhz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
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5 b4 p7 z/ Q4 ~% J) ^/ n8 L7 QThe DDR4 architecture is an 8n prefetch with bank groups, including the use of two or four selectable bank groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each of the unique bank groups. This concept will improve overall memory efficiency and bandwidth, especially when small memory granularities are used.

Additional features in development include:

Three data width offerings: x4, x8 and x16
New JEDEC POD12 interface standard for DDR4 (1.2V)
/ i. n6 n/ E* g* xDifferential signaling for the clock and strobes
New termination scheme versus prior DDR versions: In DDR4, the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.
; ~5 b, Q$ y& x& [' h, RNominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
" T. Q/ X2 B3 O) ]9 r- \$ [  ~* TBurst length of 8 and burst chop of 4
, W9 A2 b% B+ _$ [6 gData masking
DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
2 l$ D6 I  m4 UNew CRC for data bus: Enabling error detection capability for data transfers – especially beneficial during write operations and in non-ECC memory applications.
9 u( h2 t  b) N8 N2 ENew CA parity for command/address bus: Providing a low-cost method of verifying the integrity of command and address transfers over a link, for all operations.
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6 G6 q2 ]) N' d9 O7 [9 LTo facilitate comprehension and adoption of the DDR4 standard, JEDEC is planning to host a DDR4 Technical Workshop following the publication of the standard. More information and details will be announced coincident with publication.
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Looking towards the future, JEDEC's JC-42 Committee for Solid State Memories stands at the forefront of the ongoing effort to produce next generation memory device standards.
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