菜鸟求组:仿真multi-threshold cmos,实现NAND gate

ak11112222ak

source 总是出现以下问题，描述的时候已经说了是接地的了啊，为什么还是会当作断开的呢？
Circuit: *Main mtcoms file
+ W  k' p$ f3 O" _! G; B. n5 O* o
% ]5 y- D7 m" u# O4 t1 wWarning: There are nodes with less than 2 connections.
+ h( e7 J6 W( _6 g! RThe table of nodes with less than 2 connections is generated after sourcing...



0 }9 B0 z8 f9 u, O9 g' s* Z7 r/ |***warning***: the following singular supplies were terminated to 1 meg resistor
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* D- s1 C3 a) v; ksupply       node1            node2
0 O* ]9 f! v3 l* B- G, W3 q4 nvdd           vdd                  0
: u, k% R- _3 g1 uv1           a                  0
v2           b                  0
4 U( D$ Q9 _$ E1 S6 V+ o) {) u" Cv3           sl                  0


( z1 C) |' K" Z. A! ~The following nodes have less than 2 connections:
. ]9 |7 Q. u$ a' ?( h0 ^-------------------------------------------------------------------------------------
| sl                 | b                  | a                  | vdd                |
-------------------------------------------------------------------------------------
一个描述netlist的文件：


* SPICE export by:  S-Edit 15.13
* Export time:      Tue Jun 12 11:15:52 2012
* Design:           mtcoms
* Cell:             Cell0
* Interface:        VResistor
( H: Z2 D0 [- W* View:             VResistor
5 S, o5 j- i$ T; T3 J! {* View type:        connectivity
* Export as:        top-level cell
* Export mode:      hierarchical
* Exclude empty cells: no
* Exclude .model:   yes
* Exclude .end:     no
% G+ S5 S( x: R6 _* Exclude simulator commands:     no
* Expand paths:     yes
* U0 s2 X, t0 K5 T& f' Y  x% y* Wrap lines:       80 characters
* Root path:        \\en-file\users\houx\Profile\Desktop\ankun_dong hw2\mtcoms
* Exclude global pins:   no
+ H  b: f5 ?. d" _' [* Exclude instance locations: no
0 z1 }- f& v2 v/ @* Control property name: SPICE

********* Simulation Settings - General Section *********

6 V8 q- U& F2 c) U) |" e*************** Subcircuits *****************
* T2 W2 ^! P4 }.subckt INV A Out Gnd Vdd  
* w2 v+ i  p) X4 D7 F: B
*-------- Devices With SPICE.ORDER < 0.0  --------
* Design: LogicGates / Cell: INV / View: Main / Page:
4 h6 `% u; m7 M* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* q1 h( s( f. `, m+ f4 Q* Info: Inverter
* Date: 06/13/07 16:17:11
* Revision: 3 $ $x=7600 $y=600 $w=3600 $h=1200

*-------- Devices With SPICE.ORDER > 0.0  --------
; Y3 ^; O8 t5 e8 T( F0 v% OMN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=4600 $y=2600
+$w=400 $h=600
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u $
; b8 G. B& v0 j+$x=4600 $y=3600 $w=400 $h=600
7 u1 F4 a5 g' f0 \.ends
6 S( y* J- ]7 Y( T( |5 ^

$ W; I7 c1 W$ G  X+ {5 g8 M6 h
  w. s( S9 K; Q& F& G*-------- Devices With SPICE.ORDER == 0.0  --------
***** Top Level *****
, E# r- c6 F5 H7 x  I& t8 eXINV_1 SL N_2 Gnd Vdd INV $ $x=350 $y=-2300 $w=900 $h=600
% p, o( F% M9 G$ k$ u# m& W* Z
*-------- Devices With SPICE.ORDER > 0.0  --------
CCapacitor_1 VDDV Gnd  1p $ $x=3100 $y=-400 $w=400 $h=600
CCapacitor_2 GNDV Gnd  1p $ $x=3100 $y=-2500 $w=400 $h=600
MNMOS_1 Out A N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
4 T' N8 Q" M- P& B! z+$y=-800 $w=400 $h=600
MNMOS_2 N_1 B GNDV GNDV NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
1 I9 s; h) z) V" v+$y=-1500 $w=400 $h=600
% |, r, j+ X# L' U  h( f1 q" l" bMNMOS_3 GNDV N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
( W8 ^9 m7 e* Z( e+$x=1100 $y=-2300 $w=400 $h=600
MPMOS_1 Out A VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=300
+$y=-200 $w=400 $h=600
MPMOS_2 Out B VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1900
+$y=-200 $w=400 $h=600
MPMOS_3 VDDV SL Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=700 $w=400 $h=600
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********* Simulation Settings - Analysis Section *********
6 n2 F1 I" {, |8 r4 h- z# Z0 I.op
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********* Simulation Settings - Additional SPICE Commands *********
7 J" {9 Z  X$ M
- U- m2 U5 L9 ^6 H.end
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icy88

source接地的描述应该是 vdd vdd 0 0,你后面少个电压的值