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各位大侠,在给DDR2做Relative propagation delay时,发现Constraint information中除了ETCH LENTH还有一个ZALL,请问ZALL是什么?是Via等的等效长度吗?谢谢……附对DDR2 NET的Show Element:5 v, m3 m4 Z) U7 y! D0 M
! T. g& o' \( b4 WLISTING: 1 element(s), J2 z5 B2 T: j
5 U1 J! P6 D) v3 J < NET >
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Net Name: MFPGA1_DDRD23! U2 i, M# ]8 \% S) |2 L2 a, Z7 t4 q
Member of Bus: MFPGA1_DDR_DATA2 t! d: w+ f) T
& m: H! i; x" d- U
Pin count: 24 M: }0 s( \7 j, g! C6 j6 T! X
Via count: 2
- ?4 P. F/ M" Q* P/ m+ O3 e$ B Total etch length: 1964.069 MIL
( j1 a3 y/ r9 O9 x/ i/ i Total manhattan length: 1135.851 MIL
6 C5 k, k# ]- \) A4 w! g2 ] Percent manhattan: 172.92%
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Pin Type SigNoise Model Location
9 t7 f2 M; W1 ?! z2 r$ z9 U --- ---- -------------- --------+ }% c& z( ]4 A5 U: V I" c' _
U801.F9 UNSPEC (-1984.000 6603.717)' |0 ^4 M& k% g
U796.C18 UNSPEC (-2351.016 5834.882)9 t( i4 `8 `3 P+ V
9 c# v B: t3 a2 y/ y No connections remaining$ t+ L: q( B( l& U
. _, E2 x6 a. f: w0 `# c* v Properties attached to net( ^: P* \3 u5 g0 V& E3 e
FIXED% \; q/ E& O3 V3 ]2 s! U
LOGICAL_PATH = @dw5vlx_all_20120504_1800.schematic1(sch_1):mf! v* g; N+ ], `' M+ O+ s2 t
pga1_ddrd23: {; S9 V7 a+ {9 H& s
BUS_NAME = MFPGA1_DDR_DATA2
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' C1 @, E$ P2 e. f" V. l+ A Electrical Constraints assigned to net8 F) O# `. ~0 m: @' ?( [: O- l
relative prop delay: global group MFPGA1DDR_GROUP_DQ from AD to AR delta=0.000 MIL tol=10.000 MIL
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Constraint information:3 j }; q z' |% p& u; A
(RDly) U796.C18 to U801.F9 min= 1966.14 MIL max= 1986.14 MIL actual= 1980.741 MIL, G" q9 @# u' U% K ^
target= (MFPGA1_DDRDQS3P) U796.G20 to U801.B7* {/ ^0 _, J6 n4 u2 i
(-2351.016,5834.882) pin U796.C18,UNSPEC,TOP/TOP
! I: I p7 X4 Y. R- ?; u 24.812 MIL cline TOP& r' t0 z, [0 ]) O4 _5 l* g! R
(-2333.471,5852.427) via TOP/BOTTOM) b; T$ N, C# o7 z3 L( c
1917.397 MIL cline 03IS01
4 T' s8 G+ G; r (-1999.457,6588.260) via TOP/BOTTOM
9 |3 [6 H8 R% t4 E 21.859 MIL cline TOP
; [) W5 w, s5 [1 x! Y (-1984.000,6603.717) pin U801.F9,UNSPEC,TOP/TOP,Zall=16.672 MIL, U' h6 f6 m5 u/ ?2 g0 O+ q
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Member of Groups:
" N' S0 J, U3 C, V MATCH_GROUP : MFPGA1DDR_GROUP_DQ
5 \" N9 R) b' L" H: }3 F6 H BUS : MFPGA1_DDR_DATA2( Q1 H0 @6 o% R" }3 F/ |
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