本站微信 收藏本站 设为首页
 找回密码
 注册

QQ登录

只需一步，快速开始

扫一扫，访问微社区

巢课
电巢直播8月计划
EDA365电子工程师网»技术社区 › 电子技术社区 › SI仿真资料与模型 › PCB Designer’s si guide
返回列表 发新帖
查看: 1307|回复: 3
打印 上一主题 下一主题

PCB Designer’s si guide

[复制链接]
snowwolfe

23

主题

166

帖子

1080

积分

四级会员(40)

Rank: 4Rank: 4Rank: 4Rank: 4

积分
1080
跳转到指定楼层
1#
发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

EDA365欢迎您！

您需要 登录 才可以下载或查看，没有帐号？注册

x
PCB Designer's SI GUIDETable of Content
) ^* i4 P) {, I; H" U% ZBasics of SI___________________________________________________________________5 3 q, u+ i6 C: E" u. E
1.1 When Speed is important? _____________________________________________5
1 x! N# |) }# s3 i0 f9 c4 Q; J1.1.1 Acceptable Voltage and timing values ________________________________5 4 b( x+ d- I+ j; ~1 u' ^
1.2 Signal Integrity ______________________________________________________5
. F9 Z4 E/ K2 X1.2.1 Waveform Voltage Accuracy _______________________________________5 . X) a7 i# j+ r- B  r4 n
1.2.2 Timing_________________________________________________________5
5 S8 l1 O; E2 Q, o1 M1 R1.3 Speed of currently used logic families ____________________________________5 * Z- X% f2 Y) F+ ]  C* M8 A
1.3.1 Transition Electrical Length (TEL) __________________________________6 5 i( q: s) z, Q; N
1.3.2 Critical length ___________________________________________________6 , }, c. Q3 b+ \9 S: e8 D' b2 S
1.3.3 What is Transmission Line? ________________________________________6
( T9 d! g' y1 J. z3 B& w/ k3 F  i7 O8 l1.3.4 What is moving in a Transmission line?_______________________________6 0 L1 o7 M( S  Y+ O# A& y
1.3.5 Power Plane Definition____________________________________________6
$ J- ?/ B+ w: @1.3.6 The concept of Ground ____________________________________________7
3 d. c; Y! \- W- {6 b* D" ^4 _1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
( l& `! I- R' a& f3 j1.5 RLC Transmission Line Model _________________________________________8 3 t  C. V0 f8 o3 ~& O# F
1.5.1 What is Impedance? ______________________________________________8 9 p& ^* S1 @) K
1.5.2 A Practical impedance equation for microstrip _________________________8 ' J. y5 B7 E1 g) K& a
1.5.3 What is relative dielectric constant Er? _______________________________9
* P( E: K) d* D& L
! i- _' M1 I5 x8 ?$ o9 \/ l( b1 E* V4 S5 v! `! m0 I
5 t/ n+ k1 Y+ R+ g, e
2 Interconnections for High Speed Digital Circuits _______________________________10
6 y$ ?5 o3 w( b) M* a$ T
2.1.1 Summary______________________________________________________10 ! V$ L( K& R/ T3 z0 M; p3 b
2.2 Examples of dynamic interfacing problems _______________________________10
1 M+ p3 c( ]- l% [" |* s/ m2.3 IC Technology and Signal Integrity _____________________________________12 / _7 v: b; q/ t+ T
2.4 Speed and distance __________________________________________________14 : _- u: V8 T" ]) d! O
2.5 Digital signals: Static interfacing _______________________________________15
  N4 H0 |; V( N5 D. b2.6 Digital signals: Dynamic interfacing ____________________________________16
  Q. E/ o( q8 |( Q$ E% l9 A& p2.7 Review questions ___________________________________________________18 # x6 z" z5 ~1 J1 ^$ q. F+ U
% |' p: s  x. n$ R, Z. F" p& O6 Z
+ A/ X% x4 L( l; Y; o3 D# g  v  K

. v# L" u6 C0 o5 U8 k
3 Interconnection Models____________________________________________________20

  d3 l; g+ b1 c5 f$ p' f" b9 X3 ^3.1 Summary__________________________________________________________20
( {3 x! s) a1 D3.2 Reference model for interconnection analysis _____________________________20 6 }5 V4 i# L4 K* R: H
3.3 Receiver model_____________________________________________________21 ( j' |: q' @/ Z) a' f& U
3.4 RC interconnection model ____________________________________________23
7 b4 l5 m* _" w' {3 i# N7 a/ e3.5 Parameters of the interconnection ______________________________________25
/ S+ [9 b! n) Y$ a7 ^9 ?3.6 Refined models _____________________________________________________26 * k; J) ^, O* W( }- G2 k- w' b
3.7 Review question ____________________________________________________28
% i" V  v. N, ^# r. X" q4 _+ T

. c& G, H7 ^9 n4 C$ T, ~
( j+ R9 g- f, D' Y2 B
4 Transmission Line Models _________________________________________________31
6 m4 ^1 x3 ]/ b+ [$ j* k5 H
4.1 Summary__________________________________________________________31 * U( N4 Z  g2 ~
4.2 Transmission line models _____________________________________________31
4 I& Z# @9 D, \1 |4.3 Loss-less transmission lines ___________________________________________32
+ B! k4 T+ u! T. _: o4.4 Critical Length _____________________________________________________34
/ E5 i2 {5 A5 {9 D4.5 Reference transmission line model______________________________________35 2 t  f. f$ Y4 |
4.6 Line driving _______________________________________________________36 4 C8 b: K- A# @3 x6 u
4.7 Propagation and reflected waves _______________________________________37
2 t3 c) Q* S! t' s$ q$ n4.8 A sample system____________________________________________________39 - I7 E) p0 O% K, u
4.9 Review questions ___________________________________________________42
  {6 t- r4 W9 |: X" @1 `$ _5 b- q
PCB Designer’s SI Guide Page 2 Venkata

& T# I' p3 O6 A; ]7 x7 \- s4 A. b) L

: ~& I+ L/ i) k
; N5 }: W8 |$ e) d# G! p" P: y* c
5 Analysis techniques _______________________________________________________45

" X0 ]9 l8 N  X. N% ?9 E5.1 Summary__________________________________________________________45 ; i2 q/ W: [/ n& e' G7 y
5.2 Transmission time and skew___________________________________________45
5 o; Q! T) Y: R, a0 H  Z( ~$ J9 ~- o5.3 Effects of termination resistance _______________________________________46 0 R# J% U" L, [# j7 i8 w! W
5.4 Lattice diagram _____________________________________________________48 / J# ]# f; j4 p3 N) Y5 \, I
5.5 Examples of Real Lines ______________________________________________49 * b1 T0 h1 F' V& Y1 p% R
5.6 Simulation code ____________________________________________________51
1 l/ F0 ^, _6 d5 \% ]+ g. o4 t) K5.7 Examples of results__________________________________________________54
! }4 y5 G! M  }' y# Q$ E0 p5.8 Review questions ___________________________________________________55 ; f# r: _. \1 n2 }
/ t1 q1 W5 p& ^, Y1 E
, U5 y( A& X; g/ a

) _1 L! x9 z+ C$ f
6 Design guide for interconnection ____________________________________________57
% }+ i4 M; E  b; ]) q
6.1 Summary__________________________________________________________57 0 c9 E6 N( c6 `/ L( ?
6.2 Incident wave switching ______________________________________________57
: x9 J" _7 h# b8 a2 |# p' d6.3 Effects of capacitive loading __________________________________________58   S: J  Z# O& V* h. I2 n! t
6.4 Termination circuits _________________________________________________59
3 P; F5 I3 `% i  B6.4.1 Passive termination______________________________________________60
" ^# L; {8 |0 V4 S) a6.4.2 Low power termination___________________________________________61
  d8 _% u: Q' J0 s& n6.4.3 Active low power termination circuit. _______________________________61
( P1 O# Z# F- B6.5 Driving point-to-point lines ___________________________________________62
' n2 O# g* C$ L% H; m6.6 Driving bused lines __________________________________________________64
7 B  L+ g( }$ e$ {. f# Z6.7 Design guidelines ___________________________________________________67
$ o4 K9 C' [4 l" e2 N0 \6.8 Review questions ___________________________________________________67

PCB Designer’s si guide.part1.rar

1.95 MB, 下载次数: 119, 下载积分: 威望 -5

PCB Designer’s si guide.part2.rar

605.88 KB, 下载次数: 107, 下载积分: 威望 -5

分享到:  QQ好友和群QQ好友和群 QQ空间QQ空间 腾讯微博腾讯微博 腾讯朋友腾讯朋友 微信微信
收藏收藏 支持！支持！ 反对！反对！
在路上…………

下载资料威望不够？点击查看获取威望的N种方法>>
回复

举报

EDA365微信号及QQ群号！
snowwolfe

23

主题

166

帖子

1080

积分

四级会员(40)

Rank: 4Rank: 4Rank: 4Rank: 4

积分
1080
2#
 楼主| 发表于 2008-5-26 11:09 | 只看该作者
Signal Integrity in Digital Circuits ___________________________________________70 $ F) c" @2 K( i
7.1 Crosstalk __________________________________________________________70 9 a- g5 a* r2 x% i4 t% V; C
7.1.1 Summary______________________________________________________70
1 d5 q) Q- Z, {3 m/ H; h7.2 Examples of signal integrity problems ___________________________________70 6 x' k! F  e0 Y/ d, [
7.3 Simplified Model for Crosstalk Analysis _________________________________71
8 k+ o7 X8 v, Y) H$ m7.4 Forward and backward crosstalk _______________________________________74 ) c2 c  s3 t/ b9 b
7.5 Examples__________________________________________________________76
; {- h( M+ j% X* Z/ ~+ f: b* f1 |! Q7.6 Near-end and Far-end crosstalk ________________________________________80 ! \* ]& U) G/ C' T: z
7.7 Review questions ___________________________________________________81 1 J9 W# R# w0 R

2 o( p0 @+ u+ y0 y- U7 f* y/ ]3 P4 i/ |; B
# t" p7 ^6 D3 A& p) O7 e
8 Design Guide to Handle Crosstalk ___________________________________________85
& G; u* a, Y; |; U! I  Q
8.1 Summary__________________________________________________________85
& a2 j& J+ f4 J2 H9 |' N2 _4 \% V7 \8.2 Effects of Crosstalk __________________________________________________85
9 I1 {* Z6 F' d0 @  P8.3 Passive countermeasures _____________________________________________86 * |! O: `2 {' C8 X1 [: A; Y
8.4 Active Control of Crosstalk ___________________________________________92 : S, Q! t6 q! L7 i# t
8.5 Review questions ___________________________________________________94
/ M! V* ?2 ~. @8 B+ {' h
9 Ground Bounce and Switching Noise_________________________________________97

3 ~7 L1 j- u4 V! ?3 m# D# K6 P9.1 Summary__________________________________________________________97 5 R# K" ~8 v2 \% u1 w1 I( d. w
9.2 The totem pole Current Spike__________________________________________97
6 e& E" [7 x# S! |4 T9 r9.3 Current flow in the output capacitance __________________________________100 2 r2 m1 H) S6 i, e
9.4 Total Ground Bounce _______________________________________________100 ) P( a7 t4 T& Q1 D6 ~3 b
9.5 Review questions __________________________________________________105 ) ?" D) ^! w! V
10 Design Guide for Ground & Power Distribution _____________________________107
0 t& D4 a# q! X7 C. \
10.1 Summary_________________________________________________________107 + h- g' N7 z+ g' G8 P5 p
PCB Designer’s SI Guide Page 3 Venkata

- t+ i& Q1 l) Y% r' o10.2 Decoupling Capacitors ______________________________________________107
6 D" s5 H' l+ Y' ?; {10.3 Placement of bypass Capacitors _______________________________________113 4 J0 {  e- @% p8 Z8 t6 g' q
10.4 Ground and power distribution________________________________________114
# l% `+ {3 w- w- J# i% t  H  X10.5 Clock distribution __________________________________________________115
" G: M* ?/ h( c8 q: ^8 _& k6 v10.6 Review Questions __________________________________________________118
% b; T  p# G2 I. t  y- H2 V9 P: s11 Laboratory Experience _________________________________________________120 * C. R: s, \1 m& n# {. A
11.1 Summary_________________________________________________________120 % Z) c* v* ^- ^$ }. j
11.2 Aim of the experience_______________________________________________120 / k/ S( W; d3 h# u- u4 g  i3 T
11.3 Generator Parameters _______________________________________________122
% x+ L5 W7 M. D) G11.4 Cable Parameters __________________________________________________123 # g; f# z" S' a0 @7 S" f! m& x
11.5 Mismatch at driver and at termination __________________________________124 8 G, h' n+ }2 L+ B7 }( i3 x2 ^
11.6 Capacitive Load ___________________________________________________125 3 R: S. E. B- ^. M9 u2 z
11.7 7. Time-domain reflectometer ________________________________________127
& a! j4 |0 Z/ Y1 j! O. F11.8 Driving the line with logic devices _____________________________________128
) V8 j; `7 U+ Q/ c. ?12 SI Analysis Strategy____________________________________________________133 " i; ]. u2 I& T
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133 * u# t1 c% F# s6 S$ j8 f2 l
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
! s' t3 |/ @/ n9 }8 T9 D12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
9 E7 _. J, z+ @! M* b12.3 SOLUTION SPACE ANALYSIS _____________________________________135 / S4 y  b3 f) \3 r  d" d
12.3.1  H7 g( H; N' q3 i" a8 q' S
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
; O2 r5 E& N* }12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
3 i$ P2 K- |& u2 `, w) ?12.3.3: g. v( d/ W/ k7 A8 n; D; j
STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
0 g/ R7 C& t8 Q5 y! v/ p5 _0 a& `5 N0 s12.3.4
; q1 W" k% q0 p- T+ S  y- kSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136 + \5 y8 Y/ a7 L# o1 m6 D1 T
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
9 F) {( F! u0 k" Y2 N1 O12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137 2 g: g" A# Z7 `3 g+ \) z8 Y* D) g
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
" S; S% W! R* j4 d+ p12.3.8
9 R4 [$ E9 e' S, cSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
6 t% w% W2 O0 e12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138 # A# W. F% g5 M5 f, V2 d
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139 ( h- _5 a# W1 C+ G1 C: n, F
12.4 CONCLUSION____________________________________________________139 / x7 r$ d+ s! _7 S: }9 [, @7 r' ?
13 Glossary _____________________________________________________________141 : Q! ~5 w3 A: X( U; t, W: Q
PCB Designer’s SI Guide Page 4Venkata
在路上…………

下载资料威望不够？点击查看获取威望的N种方法>>
回复 支持 反对

举报

sshunhua1981

0

主题

65

帖子

-1万

积分

未知游客(0)

积分
-12020
3#
发表于 2008-5-26 16:33 | 只看该作者
了解了解

下载资料威望不够？点击查看获取威望的N种方法>>
回复 支持 反对

举报

andy.wei

32

主题

219

帖子

976

积分

三级会员(30)

Rank: 3Rank: 3Rank: 3

积分
976
4#
发表于 2011-7-8 11:30 | 只看该作者
贊一個

下载资料威望不够？点击查看获取威望的N种方法>>
回复 支持 反对

举报

返回列表 发新帖
高级模式
B Color Image Link Quote Code Smilies
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

推荐内容上一条 /1 下一条

巢课

技术风云榜

关于我们|手机版|EDA365 ( 粤ICP备18020198号 )

GMT+8, 2024-10-18 19:29 , Processed in 0.065470 second(s), 35 queries , Gzip On.

深圳市墨知创新科技有限公司

地址:深圳市南山区科技生态园2栋A座805 电话:19926409050

快速回复 返回顶部 返回列表