PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
Basics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
) n) `" m( Y9 c9 C' u4 ^: B1.1.1 Acceptable Voltage and timing values ________________________________5
& f0 `; f( c2 D% d' k. H' t& Z1.2 Signal Integrity ______________________________________________________5
& I7 O+ Q# O/ H; i& U4 ?0 H  u+ e1.2.1 Waveform Voltage Accuracy _______________________________________5
1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
' p. }; B1 k6 O1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
7 I  r( T9 w  N1.3.5 Power Plane Definition____________________________________________6
1.3.6 The concept of Ground ____________________________________________7
$ [2 M9 D9 W6 q) }0 {! N$ H1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9



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2 Interconnections for High Speed Digital Circuits _______________________________10

2.1.1 Summary______________________________________________________10
- c) }0 e" D5 H. ^! E3 L& X9 I2.2 Examples of dynamic interfacing problems _______________________________10
8 w/ O- }8 c) K7 u' E5 |2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
: A3 G- C5 C+ X2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
- r" D0 j" [7 X3 I$ k2 V2.7 Review questions ___________________________________________________18


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3 Interconnection Models____________________________________________________20

' ?9 D% ?8 h% V+ n3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
3.3 Receiver model_____________________________________________________21
4 B. Z4 S  h) y7 z* U) k2 k. l3.4 RC interconnection model ____________________________________________23
3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28

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4 Transmission Line Models _________________________________________________31

) S3 E9 E- k# v, S" [! t( `9 H4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
  P: C7 }2 ^( ]) D6 w4.4 Critical Length _____________________________________________________34
4.5 Reference transmission line model______________________________________35
4 z* K  o4 ^8 H, s4.6 Line driving _______________________________________________________36
- V' v" d, m* B/ i) n2 @4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42

PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
, Q3 P8 D9 c5 q% A. E3 l5.2 Transmission time and skew___________________________________________45
/ i: a! T, f$ k8 |5 Y* Y' M' J5.3 Effects of termination resistance _______________________________________46
5.4 Lattice diagram _____________________________________________________48
5.5 Examples of Real Lines ______________________________________________49
/ H  }: ~; |. `, R* R9 A* n5.6 Simulation code ____________________________________________________51
5.7 Examples of results__________________________________________________54
$ V& _# c9 J& Z) ^; ^' I5.8 Review questions ___________________________________________________55

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6 Design guide for interconnection ____________________________________________57

; q" ]5 H' @8 t. }  N  w6.1 Summary__________________________________________________________57
! j. i$ Y3 C; K5 X7 V) q3 I6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
  ]' s0 K1 S7 _; }: b6.4.1 Passive termination______________________________________________60
6.4.2 Low power termination___________________________________________61
7 K( ?" m: x5 `! {8 J6.4.3 Active low power termination circuit. _______________________________61
" X" D( @3 v' x) R4 S) i4 Z& f6.5 Driving point-to-point lines ___________________________________________62
6 `& L3 f/ ~7 i+ Q6.6 Driving bused lines __________________________________________________64
* u' v- e# L- C" P6.7 Design guidelines ___________________________________________________67
$ f/ {. m+ i8 s6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
. z" K4 `" w: H' k9 I5 A7.1 Crosstalk __________________________________________________________70
7.1.1 Summary______________________________________________________70
# b- ^" O6 x; L+ W& a7.2 Examples of signal integrity problems ___________________________________70
; X2 Q1 H& t: ^- b' V7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
7.5 Examples__________________________________________________________76
* H" B/ G8 b9 I! \$ |7.6 Near-end and Far-end crosstalk ________________________________________80
) H6 b. d/ m2 W, L& F; \5 l1 ^8 X7.7 Review questions ___________________________________________________81

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8 Design Guide to Handle Crosstalk ___________________________________________85

1 ~8 U6 ^( h( Y  y6 E! ?( J, ?8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
- ?+ C0 I. K' I$ ~7 d8.3 Passive countermeasures _____________________________________________86
8 g. P  Y$ F. O/ h/ ~8.4 Active Control of Crosstalk ___________________________________________92
- O  D/ i9 d& h/ |' O% l8.5 Review questions ___________________________________________________94

9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
+ _; J& k9 R9 x9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
% y# a' P5 K4 X7 U- E9.4 Total Ground Bounce _______________________________________________100
& o- @, H* t( @2 o, f! z, }9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
: U' j- i  G7 M10.3 Placement of bypass Capacitors _______________________________________113
6 q( f: j; I9 P7 h8 {7 L- E10.4 Ground and power distribution________________________________________114
5 g  v4 J0 W. s1 y3 W10.5 Clock distribution __________________________________________________115
& `2 H! E) W* k1 p. [10.6 Review Questions __________________________________________________118
( y0 ~1 u% p5 R& |! h7 k7 q3 g0 B11 Laboratory Experience _________________________________________________120
+ R7 c1 J6 ~/ N7 Z( l( ~+ U2 Z; Q' q11.1 Summary_________________________________________________________120
4 N2 i5 q5 p$ A3 r' }. w! a11.2 Aim of the experience_______________________________________________120
/ m1 f% ^$ Y; l5 c& j/ k11.3 Generator Parameters _______________________________________________122
1 F, ^5 z3 I  r9 p6 c1 [' f11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
9 G% e, J- S' W; c! L12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
. E* }" K8 P7 x# V' {" Z) r12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
! U5 n; ^* @6 W- z% L12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
4 @+ B/ E4 _# _0 b/ f4 M12.3.1
7 g( M# o" O$ x+ E9 YSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
0 K& M0 N" r7 ^+ Z. P' |6 h12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
12.3.3
STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
2 K! L5 k1 F+ q' I2 u. ^12.3.4
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
! H- G5 Q: s9 N* {, L; m. O12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
/ q$ U0 s) H2 c7 _' N- V12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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! H7 Y: E( `) y4 R, d% NSTEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
; n8 ~! A0 W5 A' ?" L1 O4 |12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata

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