Capture-Allegro最好的设计习惯

John-L

做到下面的要求,ALLEGRO NET-IN就轻松多了:
$ a9 p5 J! c* T8 d! C6 W
  n) _$ ~; r- J  P+ eBest practices for Capture-Allegro
Best practices for preparing a library for Capture-Allegro PCB Editor
flow
􀂃 Limit part and pin names to 31 characters
; Z5 T7 |4 h* n  v6 K& x􀂃 Use upper case characters for part/symbol names, part references
designators, and pin names
􀂃 Do not use special characters to assign part names, references
7 n0 ]0 u; P" u6 y; m1 odesignators, and pin names
􀂃 Do not use duplicate pin names for pins other than power pins
3 p) s9 v0 V/ e- \. q3 C0 N3 M􀂃 For multiple power pins with the same pin names, do not make some
4 Q  Q5 Z/ e3 n& lpins visible and other invisible
􀂃 Do not use "0" as a pin number
Best practices for Capture design for Allegro PCB Editor
􀂃 While defining a net list alias or a net name
( V, ?9 V+ ^' U- D$ @• Keep the maximum length of a net name or alias up to 31
9 d- V3 z9 s: ?$ B& lcharacters
$ \6 J4 b# U! @+ n5 `• Do not use lower case or special characters in a net name
$ n$ b( ]  J: {1 I1 g# x; Q7 ^3 b$ G􀂃 Avoid using "Power Pins Visible" property at design level
􀂃 Use net to connect pins
• Leave room for assigning a net name. Pin-to-pin connection
changes the net name when a user moves a component
􀂃 Run the Capture DRC command before generating Allegro PCB Editor
3 ~3 d) K/ I$ d7 ^netlist
􀂃 Set path for Allegro PCB Editor footprint before running Netrev
Best practices for smooth back annotation
  h0 n3 X- Z( x( j$ w9 o* X􀂃 Do not change design name, hierarchical block names, or reference
designators in Capture after board files creation
9 i5 f1 {  d) i- k- o" H- X# J$ c' x􀂃 Do not edit a part from schematic in Capture after board file
creation
􀂃 Do not replace cache as it changes the Source library name and part
! j% J9 s6 Q: [name, in capture
􀂃 Do not change the values of component definition properties in
$ I% H1 v  b+ ]capture after board files creation
0 \! o! l+ S, S! w6 [& q! D! b* l􀂃 Do not change Design file/root schematic/hierarchical block names
in Capture after board file creation
􀂃 Do not add or delete components to or from the schematic design
immediately after the board file creation. Add or delete components
+ [+ N' r9 D; P7 }* Yafter finishing the back annotation process
- 2 -
1 L" I( [. E; _6 R6 N+ E  @% a􀂃 Do not add any additional components in Allegro PCB Editor. Instead,
add components in Capture and take them to Allegro PCB Editor
􀂃 Do not add, rename, or delete a net in Allegro PCB Editor
􀂃 Do not change the format for reference designators for parts in
Allegro PCB Editor as <Alphabet(s)><Numeric><Alphabet(s)> or
; p: k( X% g! B2 }  h><Alphabet(s)>-<Alphabet(s)>
1 H$ I! v! c" S&#1048707; Run Allegro PCB Editor Dbdoctor before running Back annotation by
selecting the Database Check command from the Tools menu in Allegro
PCB Editor
&#1048707; Make backups of the original design before updating the design with
5 Q/ F- r2 n7 K+ m, ~# y2 R4 P2 O2 |0 ithe swap information in Capture
&#1048707; Back annotate the design immediately after making the board file.
Though it does not a mandatory step, back annotating the design
before placing components helps avoid problems in back-annotation
" M# Y) ?5 A. q8 D4 Nat a later stage.
- e0 P4 ]% a( a. AIf back annotation at this stage generates an empty swap file, you
# E& m- ^% C6 ^# T; qcan proceed with placing and routing the board file. In case any
problems are detected, you must correct them in the design file and
  s7 U5 J" {  W6 g2 Agenerate the board file again until an empty swap file is generated.

Sisic

英文版的  看不懂 請問有中文版的嗎？

xiahang

哈哈。。。谢谢分享！
下载了PDF

John-L

不知道为什麽COPY出来会有"&#1048707"之类的东东

yizhe1015

很好哦

03155001

谢谢分享

yzxujiang

努力争取

happywzb

不错
好东西

dabing715

好东西 大家分享

osinfo

7# dabing715
+ d' A. ~7 V- `- ]打开学习一下，谢啦1

hehehe

谢谢分享！

n042208

谢谢楼主

xhymsg

TKS~~~

John-L

自己顶一顶。
! J& W$ C, A) f5 ~) c2 q/ f看见好多人调网表有问题。
5 K! [4 `8 }/ ^+ M& V+ M养成良好习惯很重要。

杜晓

很好

vincent_xiao

学习了

sls_swz

学习了！顶起来！