8片 DDR Layout Guidelines and Topology:

tzwhzf

Layout Guidelines and Topology:
' l8 Y: b0 u$ _. Y9 U# ?1 zThe following are the routing guidelines followed for DDR memory interface section:
/ ]9 o$ J' {2 |2 i5 P7 U1 O( V; L1. Controlled impedance for single ended trace is Z0 = 60 ohm.
2. DQ, strobe, and clock signals are referenced to VSS.
3. Address, command, and control signals are referenced to VDD.
2 L0 B! w4 K' h) B* C8 {4. The length of address, command, and control signals are matched to clock with +/- 100 mil
tolerance.
5. DQ <0..7> & DM signals are length matched with respect to DQS with +/- 100 mil tolerance
/ N8 V6 B* }8 f+ y(byte lane).
8 |$ G$ ]  Y6 I" I& Q) \6. Each byte lanes are routed on same layer.
7. Byte lane to byte lane is matched to clock with +/- 500 mils.
8. CK & CK# are matched with +/- 30 mil and are routed as diff pair with 120 ohm differential
7 A3 ]  l, F: P- M, j* dimpedance.
9. Clock - pair to pair matching tolerance is +/- 30 mil.
5 k  i9 z5 \, H, d+ }9 _10. Trace to trace spacing is 2X and signal group to group spacing is 3X.
11. DQS signals are routed in the middle of the byte lane (DQ<0..7>).
3 b0 k6 C3 ?& S' Y12. Clock trace split point to DRAM is less than 1 inch.
13. VTT and VREF islands are separated with the minimum spacing of 150mils.
3 p4 A. X* L% }; ]9 j% E3 p14. VTT island width = 150 mil min.; 250 mil preferred.
- z+ N1 w8 c& B" w15. VREF signal is routed with 20–25 mil minimum trace.
9 \  ^. u& Z; K) Q7 z' r. l15. All signals are routed with minimum of 3X spacing between other signals
) E5 Z( C' e5 D16. Layer biasing is followed for dual strip layers.
3 x7 p* t# s" I, H, KFigure 1 shows the data bus topology and figure 2 shows the address/control bus topology.

tzwhzf

元件放置方法：
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6 v6 j! a1 }' K0 K% }数据线拓扑：

地址线拓扑：
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时钟线拓扑：
1 p" O: B9 b( m6 P) M# G, F

一粒沙

瞄 画个立体的更直观
+ L3 W% j2 a. @& A

xieyifu

谢谢楼主，学习了

wanghanq

原档

lbq211

谢谢楼主、楼上的