C@dence.SPB16.20.winnt.Hotfix.001和002所更新的内容

zlei

HOTFIX VERSION:  002
& G. d$ W* J, m: m3 g9 N========================================================================================================
CCRID      PRODUCT          PRODUCTLEVEL2        TITLE
========================================================================================================
) |+ x' {8 A: T4 w$ z" @2 o& T# a  T511865     SPECCTRA         REGIONS              Diff pairs should adhere to constraint area
, {; }: X4 o# o' |7 M: {564589     ALLEGRO_EDITOR   OTHER                The show measure command should show the actually measured po
( w2 F  @1 S1 w570861     CONCEPT_HDL      CORE                 Unconnected mark does not be removed even after wire is conne
9 R9 N4 j. `' V- G572188     APD              PAKSI_E              3-D model extract failed
# `2 P! {) I& E8 r578164     CONCEPT_HDL      SKILL                Cnskill crash during Create Test Schematic step when large pi
578874     SIP_LAYOUT       DIE_STACK_EDITOR     Stackup editor in SiP fails to add layers above and below top
( a# R* a( P$ ^7 A, {/ V6 s580315     APD              ETCH_BACK            Etchback trace fails with error "W- An etch-back trace cannot
582308     ALLEGRO_EDITOR   OTHER                Create Detail for bondpads rotated at (0,90,180 and 270) angl
594370     SIG_INTEGRITY    OTHER                Wrong description in case update form when changing preferenc
595755     CONCEPT_HDL      CORE                 Rumtime error happen when do Move Group in conceptHDL
9 ~! ^: I0 x% T& d& |3 v: [) L# h597922     SIG_INTEGRITY    TRANSLATOR           spc2spc doesn not handle inline RLGC DATAPOINTS
606620     ASSURA           DRC                  Problem with density checks in Assura
609866     SCM              SCHGEN               Schgen replaces CTAP with COMMENT symbol which causes net sho
611678     ALLEGRO_EDITOR   GRAPHICS             During Place > Manual Pins disapear if component is on bottom
615630     ALLEGRO_EDITOR   GRAPHICS             Pins are not visible when place manually is used for Bottom s
615764     CONSTRAINT_MGR   TDD                  BOM report does not filter parts with BOM_IGNORE
  U+ `8 o/ C- G/ I3 |616529     CONCEPT_HDL      CORE                 15.7 Design Entry HDL fails with Out of Memory message
616928     CONCEPT_HDL      CONSTRAINT_MGR       Net_physical_type and net_spacing _type constraints not sync'
617441     SIG_INTEGRITY    FIELD_SOLVERS        Reflection simulation fails when using wideband vias
617679     ALLEGRO_EDITOR   COLOR                The color palette will not be saved with the design unless co
617805     CIS              PART_MANAGER         Capture_crash
: m# b' i( u+ G) ~3 D% `618988     ALLEGRO_EDITOR   SCHEM_FTB            Long bus names being truncated
* E9 @5 t. m, V9 J619588     APD              EDIT_ETCH            Poor routing performance. 5 second delay after each mouse cli
619691     SIG_INTEGRITY    FIELD_SOLVERS        Problem of EMS2D by using FreqDepFile
9 K% E2 d" s/ @: ]9 P619867     ALLEGRO_EDITOR   DFA                  DFA_BOUND_TOP shape doesn't display DFA Audit conflicts
620359     CONSTRAINT_MGR   CONCEPT_HDL          ECSet and Netclass definitions lost in the FTB process
620424     CONCEPT_HDL      CONSTRAINT_MGR       CM restore from definition of subblock removes ECSets defined
. M5 e4 l7 \5 i! ]5 m8 @620700     ALLEGRO_EDITOR   PAD_EDITOR           Shape has bigger void on Y direction for Oblong SMD Pads
620868     SIG_INTEGRITY    PAKSI_E              Wirebond material conductivity is not used by PakSI, only a d
620895     ALLEGRO_EDITOR   DRC_CONSTR           About error message of cns_design command.
620924     CONCEPT_HDL      OTHER                PDF Publisher 16.1/16.2 can not output some Japanese characte
# i' h6 U$ O; p* r0 J. y621156     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Rule for 揟race Minimum Angle to Pad?not showing all th
4 D$ a4 y# |* ^- T$ b3 O621163     SIP_LAYOUT       ASSY_RULE_CHECK      Ambiguity about the how is the 搒tart of the wire" defined in
9 K) N8 u. O6 a( E621298     CONSTRAINT_MGR   UI_FORMS             PCB SI crashes when importing a constraint file into Constrai
# J1 h( u' c# W- [1 F, D8 |621315     ALLEGRO_EDITOR   PLACEMENT            Getting wrong component when using Place replicate unmatched
621848     CONSTRAINT_MGR   TECHFILE             techfile write fails with Failed writing object attributes
8 v* a4 |2 r9 S( y- H% @621867     ALLEGRO_EDITOR   TESTPREP             Transcript window randomly locks up when running TestPrep
. Y' y9 [  L8 [. v' U621901     SIG_INTEGRITY    OTHER                Incorrect extracted via drill/pad diameters and missing inter
7 R) n: J3 p/ q: ]622010     ALLEGRO_EDITOR   DATABASE             Undesired openings in Negative shape
& Q% b8 _6 F9 W622062     CONSTRAINT_MGR   DATABASE             Importing dcf file at system level crashing the Allegro PCB e
622156     ALLEGRO_EDITOR   SHAPE                Thermal/Anti value producing incorrect void sizes
622450     SIG_INTEGRITY    SIMULATION           Field solution failed
; z/ S% k1 G4 a9 Q- J622466     ALLEGRO_EDITOR   COLOR                layer priority in 16.2
622566     ALLEGRO_EDITOR   SCHEM_FTB            Replacing the components of same refdes on board after import
2 n6 }1 i/ D0 p' f) ]% G) V$ e5 W622700     APD              PLATING_BAR          Plating Bar Check is highlighting Nets that appear to be conn
622862     ALLEGRO_EDITOR   ARTWORK              Allegro crashes when we enter a value in the field file size
) c8 [: T7 M6 C4 r/ t622989     SIP_LAYOUT       IMPORT_DATA          Type of Wirebond die changed after die import
; I  t% z  [& X- ~* I$ g623182     SIG_INTEGRITY    FIELD_SOLVERS        Extract topology crashed
623300     SIP_LAYOUT       3D_VIEWER            Wrong placement of Solder Mask Bottom in 3D view file
623384     ALLEGRO_EDITOR   VALOR                Valor output showing padstacks on 45 degree angle wrong in 16
623489     ALLEGRO_EDITOR   EXTRACT              Allegro tools Report etch length by pin pair takes forever to
% s" {5 Y! q% I# |. ?$ o7 z623529     ALLEGRO_EDITOR   EDIT_ETCH            Manual tandem diff pair routing has been lost in the 16.2 rel
623536     F2B              PACKAGERXL           packager fails with memory allocation error
623673     CAPTURE          OTHER                Unable to get capture window size to full-screen in dual disp
623701     ALLEGRO_EDITOR   OTHER                'Analyze' menu missing when opening Allegro PCB Editor L - Pe
7 ~8 g3 x9 u: A0 R, P1 l0 }6 R623738     CAPTURE          PART_EDITOR          Create part from spreadsheet is not working correctly
7 o' {$ {. m" m- O) G3 }623740     ALLEGRO_EDITOR   OTHER                Can we use variant.lst file as list file in find filter
% Y( d/ X$ G8 q, d) M5 e623745     CAPTURE          OTHER                Capture crashes when the user tries to place markers
623813     SIP_LAYOUT       WIREBOND             Add wirerbond only is not working in this case with a bondfin
623830     ALLEGRO_EDITOR   MANUFACT             backdrilling is drilling through component pads on the bottom
624048     ALLEGRO_EDITOR   OTHER                Viewlog for Export to 16.01 is not closing from any of the 'C
" {' H4 T7 q; Y9 x$ m. H8 Z- W624223     ALLEGRO_EDITOR   GRAPHICS             disable_datatips variable is busted
1 ^& P, v4 V1 c4 I) z624495     ALLEGRO_EDITOR   SHAPE                Static shape did not void to drill holes
; ]7 T4 \3 ^  w  j) |624599     SPECCTRA         ROUTE                PCB Router hangs on route of design
624653     APD              BGA_GENERATOR        BGA Generator fails at 400um pitch
624812     CONSTRAINT_MGR   ANALYSIS             Importing dcf at the system level causes RPD constraints not
, g" U4 ~- b) B  F+ ^3 R624888     ALLEGRO_EDITOR   DRC_CONSTR           Regions and RCI's Cset not working as expected
624958     ALLEGRO_EDITOR   EDIT_ETCH            Slide in region is changing etch to min line width
9 W" [, z% n7 r$ U625251     ALLEGRO_EDITOR   COLOR                16.2 Linux allegro - new subclass created does not reflect in
625273     APD              IMPORT_DATA          Import a .mcm into SIP in order to edit the die pins. Edit ->
: \) ?' w* t9 A625279     APD              DIE_EDITOR           die text in fails when the function name is >31 characters wi
& S! H# s3 k1 Y625304     SIG_INTEGRITY    IRDROP               Need a better understanding of absolute current values report
625367     ALLEGRO_EDITOR   DRC_CONSTR           drc_fillet_samenet does not work correctly
625551     ALLEGRO_EDITOR   SHAPE                Dynamic shape is not voiding to route keepout correctly
8 \5 t1 B1 h7 Z; g- t" F, w625852     ALLEGRO_EDITOR   DRC_CONSTR           Some buses in CM are disappeared after import CIS 3 .dat netl
) {) Z7 T5 b+ B7 l& E625885     CAPTURE          DRC                  Report misleading Tap connections check for DRC reports error
625972     CONSTRAINT_MGR   TECHFILE             techfile import fails with Failed writing object attributes
626630     CAPTURE          NETLIST_ALLEGRO      Capture 16.20 hangs endlessly but Capture 16.0 prompts result
/ w+ I6 |& ]9 c5 y( z$ J$ d626669     SIP_LAYOUT       OTHER                16.2 radial router find filter does not have option for bond
7 ]. C7 m+ M4 T. H* u: v626671     SCM              OTHER                Adding signals in ASA is taking too long
627228     ALLEGRO_EDITOR   MANUFACT             Dynamic Fillet is disappered, when use slide command.
+ }  J. G; ^' O& h0 G3 l* ]627289     SIP_LAYOUT       DIE_GENERATOR        Pins connect at the same net name after Die Text In
627864     CONCEPT_HDL      EDIF300              EDIF c2esch crashes
& [) n) ?! S; t" o5 P# e0 o4 Z0 Z628169     ALLEGRO_EDITOR   OTHER                write command changes design name in constraint manager
628220     SIG_INTEGRITY    SIMULATION           Reflection simulation failed with filed solver "EMS2D"
: o& q- D8 }- `: z* H. R628261     APD              OTHER                no "Tangent Via Line Fattening" in APD products
628922     APD              REPORTS              Metal Area Report shows 0.00 on one layer
$ ]0 w' e4 O0 R; S" P1 WHOTFIX VERSION:  001
) P$ W6 P* l  s9 h7 a========================================================================================================
7 Y5 j+ k3 k8 W1 Y5 e& b: k/ ^6 _CCRID      PRODUCT          PRODUCTLEVEL2        TITLE
+ h6 m& w8 `" _0 S2 v========================================================================================================
191020     ALLEGRO_EDITOR   SHAPE                Shape edits results in same net DRC being reported.
! G7 ^9 d. s5 s! \! I230469     ALLEGRO_EDITOR   SHAPE                Allegro improve performance of Dynamic Shapes
* C5 L' o3 g7 r% o  |: f295039     ALLEGRO_EDITOR   DFA                  Allegro DFA to be enhanced to include height
346863     CIS              DESIGN_VARIANT       Variant View mode is not working for multi-section parts
400036     CONCEPT_HDL      HPF                  nihongo_vector_font should be listed in the Plot Setup GUI
+ @- {: q, Y8 |410092     CONCEPT_HDL      OTHER                The Imported sheets loses the write permission for the group
415462     CONCEPT_HDL      MARKERS              The SPB157 Markers does not normally display the Japanese fon
: ~5 H- U9 ^% D501802     ALLEGRO_EDITOR   GRAPHICS             When hilighting parts or nets the system is inconsistent on z
1 d; ?! n! E* b503526     SPIF             OTHER                SPIF is NOT defining class for class to class rules.
511175     CONCEPT_HDL      CORE                 Copy All causes - No object selected error
5 ]1 p# {! J, l  ~+ ]' q, b. h526774     LIBRARY          DEVELOPER            Pin抯 text size goes back to default size after change pin na
533536     CONCEPT_HDL      OTHER                The font used in published PDF is not identical.
# ~; |2 C9 W  i/ O* F( S537769     CONCEPT_HDL      CORE                 Sporadic behavior of DE HDL toolbars for adding components ge
544519     ALLEGRO_EDITOR   MENTOR               mbs2lib Generating extra "b" version of footprint during tran
. G( M7 a, ~6 ~8 Q551528     LAYOUT           OTHER                Layout2Allegro L2A translator not translating reference desig
551614     SIG_INTEGRITY    IRDROP               Import and export of IR-Drop setup
+ C- I( y2 F! x" w0 u1 @3 ?4 F4 e) y552127     LIBRARY          LIBUTIL              When -lib is missing from con2con PTF files get re-written in
4 w1 L& B( v& E- h4 d560417     ALLEGRO_EDITOR   OTHER                Part Logic does not read part row from ptf file and assign in
564954     CONCEPT_HDL      CREFER               Crefer attaches $XR property to other $XR on RHEL.
5 R) c5 w2 D6 n( w  `3 ], C( o! A565798     CIS              DESIGN_VARIANT       all the sections of mult part package are not coming as DNS i
5 l; v$ j! Q% L6 `$ X7 ~! ]2 p571627     CONCEPT_HDL      CONSTRAINT_MGR       cmuprev fails to synchronize constraints on low assertion vec
577915     CONCEPT_HDL      ARCHIVER             zero folder is not archived how the archiver is working ?
4 e. y7 t/ T4 @8 N7 u) {581446     LAYOUT           TRANSLATION          L2A fails with pin numbers do not match between symbols from
0 t* v) t6 Q. o1 `7 ?: n583891     ALLEGRO_EDITOR   MENTOR               Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
1 g9 }" K6 R0 H$ m7 z" R$ ~1 n586998     ALLEGRO_EDITOR   PLOTTING             Board shifts towards top left when plotting at higher resolut
$ {1 [* Z/ ^) x6 K/ |587870     ALLEGRO_EDITOR   PCAD_IN              Import PCAD fails due to dupliate pad name.  Caused by a peri
588949     CONCEPT_HDL      CORE                 Importing schematic pages from another project crashes Concep
7 p7 E) w' o) N8 ~2 f; l' U, E592340     ALLEGRO_EDITOR   MENTOR               MBS2LIB not creating the correct shape in symbol
8 v6 n" [: s; i; v3 X7 A2 W" s596530     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro Translator removing/renaming reference design
596638     ALLEGRO_EDITOR   EDIT_ETCH            The timing meter indicates untruthful violation
596716     PSPICE           DEHDL                Flag error due to part pin mismatch while create netlist
4 A8 i+ g% a( x# g597685     ALLEGRO_EDITOR   SCHEM_FTB            ratnest are out of date error in DBDoctor after import logic
597937     ALLEGRO_EDITOR   PADS_IN              Request PADs_in to translate keepout areas
7 g# |, D( A8 R" E598575     ALLEGRO_EDITOR   OTHER                During Split plane should it use settings regarding fill styl
( A7 R% t9 @0 I1 `2 a598814     APD              WIREBOND             bondfinger does not move relative to its origin using ipick
599823     CONCEPT_HDL      CONSTRAINT_MGR       Lost ref to dml-lib causes loss of cm data even if the refere
- y, l/ S% T; G& s599886     APD              EXPORT_DATA          bodygen batch tool is failing to generate .css file
603425     SPECCTRA         PARSER               Do file fails Syntax error in command unexpected end-of-line
9 S1 W4 F) i/ L  o, U4 _5 A$ j$ t0 i+ J603987     APD              OTHER                Offset via generator should ensure pitch distance is met or e
604377     SCM              PACKAGER             Output board name containing a dash causes scm crash
( h" B5 a5 N, O3 ?+ x" h  H604614     CONSTRAINT_MGR   OTHER                netrev is unable to update the Canonical paths with the new d
/ U: B- o4 h+ b3 f604794     ALLEGRO_EDITOR   PAD_EDITOR           Replace Padstack reports error pad missing not true.
& {' t  ]" k2 d' _& o+ p4 v605169     ALLEGRO_EDITOR   OTHER                Can design_compare handle swappable pins?
606586     ALLEGRO_EDITOR   INTERFACES           Multiple drill in padstack cannot be shown in Pro/E IDF
607217     APD              IO_PLANNER           wirebond die replacement from IOP
5 g3 `4 V0 U2 l# ^* x607222     APD              WIREBOND             auto wirebonding creates wirebond with DRC
607644     ALLEGRO_EDITOR   MANUFACT             Enhancement to increase the IDF export ''default package heig
3 J* C  C  r9 N8 }607718     CONCEPT_HDL      HDLDIRECT            HDL Direct Errors reported while generating simulation netlis
608233     SIG_INTEGRITY    FIELD_SOLVERS        Convergence errors with analytical vias when drill size is 1
' U* N7 G5 a+ b- S( Q# E609549     ALLEGRO_EDITOR   INTERACTIV           Mirror Geometry command to change BB Via's layer.
610028     SIP_LAYOUT       IMPORT_DATA          De assign NC nets during aif import
4 [1 c- b/ `- n* @: f) W610134     CONSTRAINT_MGR   INTERACTIV           Cross-probing from CM to Allegro no longer works on system le
7 m6 [9 p" r, J6 x  i2 O610276     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro translation is failing with error.
6 o0 L/ a7 o: f$ S( s3 n: h610482     ALLEGRO_EDITOR   SCHEM_FTB            Netlist swapped net names on 2 pins causing shape to lose its
8 x% y3 H' N7 u4 ]2 J( Y6 R610681     CONSTRAINT_MGR   DATABASE             An exported constraint file can not be re-imported in V16.01
8 z4 S8 f! z2 O3 s611260     ALLEGRO_EDITOR   DRC_CONSTR           Routing a diff pair it does not follow Physical line width se
611425     ALLEGRO_EDITOR   MENTOR               mbs2brd crashes when importing Mentor
611697     SIP_FLOW         SIP_LAYOUT           octagonal bumps have offset in SIP compared to the chip view
3 p# P$ I* k% f! b. ?+ m, R611807     APD              WIREBOND             Duplicate paths created on wirebond import for some cases.
611856     CONCEPT_HDL      GLOBALCHANGE         Ref des deletions after runnning Global Change to change $LOC
611874     CONCEPT_HDL      OTHER                Crossprobing one symbol in Concept using Occurence edit mode
612088     PSPICE           DEHDL_NETLISTER      Fail to create the netlist for G value expression
612195     ALLEGRO_EDITOR   DATABASE             Adding layers to the default cross section causes phantom tex
612237     ALLEGRO_EDITOR   SKILL                axlFormColorize does not change the full background area of a
$ h5 p; l; W* C5 ]; {1 {612299     APD              DEGASSING            Degassing static shape creates voids inside of voided areas
612560     CONSTRAINT_MGR   OTHER                Diffpairs don't show the CSet assigned through Net Class
612587     APD              WIREBOND             Unchecked Allow DRC option creating disconnected wire bond.
' J# G4 G% n. P612884     SIG_INTEGRITY    SIMULATION           When using ViaModel
. r; i+ y! Q1 U8 Z612914     ALLEGRO_EDITOR   EDIT_ETCH            Centered via option in fanout command not available when swit
612939     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Continuous Solder Mask check problem
613553     CONCEPT_HDL      EDIF300              edif schematic writer crash on this design
6 K- H& O7 e7 e613565     ALLEGRO_EDITOR   EDIT_ETCH            Allegro Editor Differential Pairs are routing incorrectly
613736     SPIF             OTHER                Spif fails to write class data
613990     POWER_INTEGRIT   INTERACTIV           PI is crashing during capacitor selection
614278     CONCEPT_HDL      EDIF300              pin text note and flag are not visible on reloaded edif file
8 a' ~8 j, |- N& O" G0 ]614371     SIP_LAYOUT       WIREBOND             Any wirebond command crashes the application
614407     POWER_INTEGRIT   INTERACTIV           PI crashes when editing capacitors
; x; y/ W$ x! f2 l' M+ i614727     SPECCTRA         GUI                  Allegro PCB Router can not process the dsn and rules file for
614972     ALLEGRO_EDITOR   SKILL                axlCNSSetSpacing does not change the value of the "testvia to
615144     SIP_LAYOUT       3D_VIEWER            die placement does not change with changing in soldermask thi
' ?  i3 i, X0 K) g: i5 n615431     LAYOUT           TRANSLATORS          padstack names are crippled or renamed if it has over 18 Char
615506     APD              MANUFACTURING        Sort by die pin location for Manufacture Doc Bond finger brok
615745     SIP_LAYOUT       DATABASE             Move die symbol with stretch etch on is disconnecting wires f
/ x: j9 u7 g% D2 x* T: X615816     SPIF             OTHER                Allegro match group members not translating to PCB Router; mi
  x, u) u& a+ l+ X; ?7 k616104     CONSTRAINT_MGR   OTHER                allegroTechnologyFile XML format issue
& y; |- v( F; t5 `$ _616122     LAYOUT           TRANSLATORS          Protel to MAX translator problem with package outlines and re
616404     ALLEGRO_EDITOR   OTHER                Design compare fails with message "Invalid input argument" wh
3 G7 z" G3 y! |# [; J$ C- O616713     CIS              PLACE_DATABASE_PAR   property name with "&" charecter in access database causing c
$ w- P9 U5 v, R; a0 M! ?! ^% k616818     SCM              PACKAGER             BOMHDL -type scm fails on schematic block
& j; K0 h% f* b! k% `4 {/ }616907     SCM              VERILOG_IMPORT       scm crash during Get Module Name
- h- W5 U9 J4 L; s6 M! ^617058     APD              WIREBOND             wirebond space evenly does not work for fingers on power ring
, r' S- I" t5 h9 q: s2 K. y617083     ALLEGRO_EDITOR   INTERACTIV           Windows tabs hangs on Linux
6 L, y/ B; ]$ i8 \617236     ALLEGRO_EDITOR   SHAPE                Editing a shape in a void causes the bigger shape to drop seg
617351     CIS              DBC_CFG_WIZARD       XML writer fails if DBC location doesnt have write permission
# W1 R9 c; u9 Z( W" ?, |617515     SIP_LAYOUT       OTHER                Be able to invoke Velocity from cdnsip
617761     LAYOUT           TRANSLATORS          Value property for Library symbol of Orcad Layout is not tran
617890     SIP_LAYOUT       WIREBOND             Push and shove on Bond fingers with multiple bond wires cause
6 S5 ]9 ]7 C/ y( t9 G" Z4 K* X618184     APD              OTHER                database diary on unix/linux
618201     ALLEGRO_EDITOR   OTHER                Dynamic fillets take a long time to complete
% r& w& u( k; r+ G7 w% @/ [618545     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes when we place a package symbol for Jumper usi
. U  d6 j4 W# E) U5 I6 }618610     ALLEGRO_EDITOR   MANUFACT             Delete a cline seg creates a fillet
618651     SIP_LAYOUT       IO_PLANNER           Bondfingers and die are shifted every time an update package
4 V3 {; C8 }4 J, d7 V# V618712     ALLEGRO_EDITOR   EDIT_ETCH            Shove mode is not working on Diff pairs in PCB Design L
  \1 G, V! I$ ^' I) o618836     ALLEGRO_EDITOR   SCRIPTS              Allegro does not interpret recorded macro script files proper
5 s; a5 ?* p; p( D3 t% j618946     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes while using Place Manual -H
0 A0 K( o  o  B5 V618984     ALLEGRO_EDITOR   COLOR                Layers on Allegro Canvas does not match Color Dialog Box
2 v3 u2 Y, @7 ~: Q: w1 R- B619007     ALLEGRO_EDITOR   SKILL                Skill command does not accept spaces in file path/name
! ]  g( ~9 i8 A  ]) t, N8 \619033     F2B              PACKAGERXL           Pinswap lost on backannotation
, q+ P3 w  S; j* N2 }6 q- h, l/ g619268     POWER_INTEGRIT   SIMULATION           IR-Drop can't sees via on pad as open
$ z, U$ f2 [  |# t1 {! t# Q619356     CIS              FOOTPRINT_VIEW       Footprint preview only from 1 directory in Capture.INI
  s  e0 k1 r) M+ Z3 W' L619712     ALLEGRO_EDITOR   EDIT_ETCH            Unable to route in the Bubble Mode for Partitioned board
! \' A9 k. b# F$ J$ {- S: M0 V619773     ALLEGRO_EDITOR   DATABASE             Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
620064     CONCEPT_HDL      CONSTRAINT_MGR       Loosing Diff pair constraints from lower blocks when packagin
622132     CAPTURE          NETLIST_ALLEGRO      Incorrect ALG0078 error for complex hierarchical design