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本帖最后由 紫菁 于 2017-10-13 13:10 编辑
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) I3 T7 A J2 Q$ NPrequalification trials
1 t+ _7 t: F4 v3 GMost of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.7 W$ J! H% r/ b
: i4 k! D6 t) d9 ^Datasheet 建議你重置試試，看 MCU 能不能重新跑起來，然後觀察會不會再度發生。% U# y# B8 @% f; v$ Y# V' \
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To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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AN1015 教導你利用一些 Timer 和 WatchDog 等技巧，降低意外掛機的情況發生。! o6 j$ d: d- y& o- I) k- i& Y
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3.11.4 Independent watchdog (IWDG)* I# T5 m* U- X# v4 b$ N
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.2 g; G) p) S0 q7 U/ V) n5 H! P
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看門狗（IWDG）使用 40KHz 獨立的時鐘源，較不容易受到其它因素的影響，可利用它來防止掛機，或是用來找出掛機的原因。, r( w1 @$ n7 _/ }. n I7 Q4 h
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发表于 2017-10-12 21:20
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发表于 2017-10-12 22:44
