A closer look inside SK Hynix's 1st high bandwidth memory

pjh02032121 · 发表于 2017-4-11 20:37

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Korean memory chipmaker SK Hynix finally showed its high bandwidth memory (HBM) module in a downstream product after announcing it early last year, claiming it to be the world's first 8Gbit module developed using 2Gbit, 20nm node, DDR4 SDRAM. The HBM module appears in AMD's Radeon 390X Fury X graphics card.

We at TechInsights have a few of the Fury X cards in our lab and its GPU unit is shown below in Figure 1. The GPU die is seen in the centre of the module with four Hynix HBM memory modules arranged around its perimeter. Both the GPU and the HBM modules are flip-chip bumped to a UMC fabbed interposer. This interposer is, in turn, bumped to a laminate substrate. The GPU is massive measuring in at 23mm by 27mm large, and is believed to be fabricated using TSMC's 28nm HKMG process.

The HBM uses through silicon vias (TSVs) to connect the DRAM dies and base logic die together, and this is a fairly new technology for DRAM. Samsung has a 20nm DDR4 with four stacked DRAM dies with TSVs, but this part is not a wide I/O device, nor does it contain a base logic die. Hynix's HBM has a 1,024-wide bus qualifying it as wide I/O. It employs a base logic die as an interface between the four DRAM die stack and an interposer that supports both the HBM modules and the AMD GPU. The HBM can be considered 3D packaging, while the laterally spaced apart layout for the GPU and HBM modules on the interposer makes for a 2.5D package.

Figure 1: AMD Fiji GPU with Hynix HBM memories (Source: Detailed Structural Analysis of the SK-Hynix HBM, TechInsights)

Figure 2 is a SEM cross section of the Hynix HBM module showing the four DRAM dies, the base logic die, the AMD interposer and the laminate substrate. The bottom three DRAM dies have been thinned, while the top DRAM die is considerably thicker. The thicker top DRAM die is likely a deliberate design feature, and is possibly being used to add mechanical stiffness to the HBM module. Microbump structures connecting the dies together and to the interposer are just visible in this image.

Figure 2: Hynix HBM memory (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

The TSVs used to connect the stacked DRAM dies together can be seen in Figures 3 and 4. A via middle process is used to form the TSVs, where the wafers have undergone their front end of line processing (FEOL) to make the transistors, their contacts and pre-metal dielectrics. A reactive ion etch was likely used to make the TSV openings. The vias have a slight taper, with the top portions of the vias, nearest the active circuitry, being slightly wider than the bottom portions.

Figure 3: Stacked DRAM dies and TSVs (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

The bottom portion of the TSV (Figure 4) is seen contacting the copper microbump, while the top portion of the via contacts a copper interconnect in the DRAM die.
The topmost DRAM die seen in Figure 2 also contains TSVs and these are seen in the bottom DRAM die in Figure 4. Figure 4 has been inverted so as to place the active circuitry on top. The bottom die has vias that penetrate approximately 50μm into the silicon substrate indicating that the via etch was performed from the topside of the die. The tops of the TSVs lie beneath the die's bond pads, which tells us that the via openings were made before the back end of line (BEOL) processing.
Hynix disclosed a via middle process for their HBM in two papers (Electronics Components & Technology Conference 2013 and VLSI Tech. Digest 2014). The TSV openings are formed after the tungsten contacts to the gates and source/drain regions are made, using a Bosch TSV etch. An oxide liner is then deposited along the via sidewalls, lined with a Ta-based barrier and Cu seed layers, and filled with electroplated Cu. A thermal anneal process is used as a Cu stress relief. A CMP and etch process is used to thin the backsides of the DRAM wafer and expose the Cu TSVs. The backsides of the DRAM wafers are then passivated with oxide, followed by the formation of the backside microbumps.
We would expect to see scalloping of the via sidewalls that is typical of the Bosch etch and Hynix has commented on the need to keep the scallop diameter to less than 30nm. Our initial SEM cross sections of the vias do not show the expected Bosch scallops, indicating that Hynix has a great etch recipe.

Figure 4: TSVs and microbumps (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

The top portion of the TSV along with some of the DRAM metal interconnects is shown in Figure 5. The TSV hole is seen passing through the silicon die and the overlying inter-level dielectric (ILD), stopping on the underside of the copper metal 2 (M2) line. The via middle process is confirmed by this oxide liner extending from the via opening up into the ILD.

Figure 5: Top portion of TSV (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

Stacking the DRAM dies and interposer would seem difficult to do, but Hynix provides a hint of how this is done in their 2015 paper (J. Solid State Circuits, 2015). Here, they describe "stacking dies on the wafer, flipping and testing." Figure 6 shows the ends of the dies in the HBM module and we can see die underfill extending out past the bottom DRAM die and from the top most DRAM die. The middle three dies have their ends pretty much coplanar, and their underfills ending with the die edges.
This would suggest that the three bottom dies were stacked together at the wafer level then diced as a group. The top most die is more than twice as thick as the lower three dies and was likely diced and tested before being attached to the DRAM stack. We suspect the four-die stack was then attached to the base logic die.

Figure 6: HBM package cross section (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

We estimate that there are nearly 2,100 TSV pads on each of the DRAM dies and a block of them are shown in Figure 7. A large fraction of these will be used for power, ground, addressing, data I/O and redundancy, but a number of them are used as control signals for testing the TSVs.

Figure 7: DRAM die TSV Pads (Source: Detailed Structural Analysis of the SK-Hynix HBM, TechInsights)

Hynix's two papers (J. Solid State Circuits, 2015, IEEE Solid-State Circuits Conference 2014) discuss their testing strategies for the HBM. And my understanding of their papers would suggest that each of the DRAM dies has its own TSV select circuits, current sources and e-Fuse structures, while the base logic die contains the test circuitry for selecting the individual TSVs and measuring their electrical resistances.
Since each die has its own e-Fuses, I would expect Hynix to block out a bad TSV on a single die using an e-Fuse and substitute in a good TSV from a set of redundant TSVs. This avoids the need to block out the complete vertical stack of TSVs if only one is bad, reducing the number of redundant vias that would otherwise be needed.
This is all very clever and I am still reading through their paper (Dong Uk Lee et al. A 1.2 V 8 Gb 8-Channel 128GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits J. Solid-State Circuits Vol 50. No. 1 Jan 2015) in order to understand how this all works.
And hats-off to Hynix for delivering the world's first high bandwidth memory. If you are interested in analysis referenced in the above article, you can find out more by clicking here for the SK-Hynix HBM Detailed Structural Analysis, or here for the SK-Hynix Package Analysis; lastly, here for the Samsung DDR4 with TSV.