我用cadence16.5 ConceptHDL设计原理图,完成后道pCB,我使用的Top-down式原理图设计方式 2 _1 E2 w/ M. Q" g+ y导PCB时提示“Connectitivity server is unable to load design. The .xcon file might be missing or incorrect. Your design needs to be netlisted in 16.4 or later version of Design Entry HDL" * A- Q+ E' k( G2 d+ q, k8 E+ a# x) f8 i
这个是由什么问题导致的?; n# M8 }3 {5 W( H3 I! Y