|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
DATE: 05-28-2016 HOTFIX VERSION: 071
! F: i3 X' [# |: u: ~===================================================================================================================================0 U6 p$ j% A9 N/ x9 c" _
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 N. \* t, m" G0 m
===================================================================================================================================
7 D m$ \1 w+ K% g" e1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets
1 ]* o. ?7 C$ b1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package9 O& |0 @2 ?7 c) L: E, r* k
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
" D3 Q5 ?8 v' v% z5 ^6 V& W+ w4 O1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly6 j9 l0 u3 C4 H$ h
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.' H; t7 r3 A# S
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.7 V" k: Z) J* _; a
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
: V' y& [' e- m) D1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
) C" L9 P; [7 d! r% }8 m: S1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
/ D- V8 ~8 K0 s% Y- d1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library3 w* T& l- z; i0 O
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG0 p. j* [# |) x/ q9 { u$ M2 T
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
- S/ P1 d' V0 T5 H1 i- [- j1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
J- I. {2 ]" J L1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
; I4 _8 L2 d& H. J1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters+ }/ O$ C, R2 Y7 e* a( h6 T& o4 _
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC5 K& Z4 D' T" T4 p4 O2 ?
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins- y4 c7 z$ S2 v2 `9 u
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas. J4 ]4 Y2 Z6 y+ B; y# ]; _
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
0 }% L. s2 b" [2 v1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete* U8 G$ W" a4 z$ E5 g/ @) k
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
# O( R* W& X9 j' I$ U1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
, f( V+ u# r4 w3 N5 L1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
: P9 n4 R% Q8 w: P6 T7 w1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'7 d( u- Y6 s. P5 _: I F- ?' q. h
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
E. f1 Q# R3 _3 I3 \1 j, K% t. `1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...; R; L; s( z/ w, ^% a
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager* |( ~7 u9 I" M9 u! [
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
& d9 g. U- Q4 f; R H6 \; z Z1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property
9 ?, e. B7 k* x3 ?; S+ n1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only+ [6 i7 o ^1 Z' a
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
) A& J/ b D5 L: q; u* I7 h1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
- Z+ Z: ?& s S! I# Q9 p1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
# z" Y l, G1 m$ |( e1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings" B& R4 n0 r9 P9 p, ^. F1 N
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'$ Y# k! D$ k4 ~, G
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
0 j4 {$ A$ U. R$ x$ o4 E9 m
& }& t9 l0 o, k: j: DDATE: 04-22-2016 HOTFIX VERSION: 069
/ P! m( _ `4 l, j===================================================================================================================================
# w* q' e, {# O( [' DCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 E/ d K( ~, v8 Q3 k5 a===================================================================================================================================
2 I4 t7 [! z5 H$ \- B3 |1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
4 K* V8 K6 _9 I2 I/ x9 E- S1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode$ N5 G d! @* n$ n
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
) b, Q2 d# D' O1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol% r/ T9 O) p8 @* s
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
) V' B' E1 d/ o5 Z1 F3 X1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute& J0 t; m3 q) z5 T9 D0 h
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
: B- a& ^ v- ^1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
8 U: C6 r) L7 F5 T1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed4 \; S9 s7 ]4 A: I& d9 G0 C( o0 ^
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
) i `% R6 j& k# X w1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
: h' x/ S7 C" u( _1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork; ^* |( J0 n# \& E; O; w
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
+ w% ?# o# {- o, u, S/ D1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
* {+ ]' F0 Y! z5 r& P! g1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines4 h# x7 @ y. u. U; Q/ L
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
2 e* o. L- A7 v! {4 Y; [- Z1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro6 D# a+ M6 d0 u
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups4 d& W2 B( T4 _% P+ T, ^" y
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
) u/ p, i9 s5 \/ G1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes" X+ Z8 B! s5 v- S
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted7 ] ^/ u$ y! p0 D' Z5 Z3 F m G
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die G+ e2 b V1 ]& E9 l1 S
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
& f2 [, \, L2 a* `4 f7 O) T: p. K1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error
, N- \9 F: i. t8 z! L9 E1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.
, Q# d$ z- U% R q* n
4 T" w' s M4 K/ b7 YDATE: 03-23-2016 HOTFIX VERSION: 068
' ]0 V7 f' {9 c5 k! j2 v3 u" n===================================================================================================================================
5 z0 i( |" L. I# K$ zCCRID PRODUCT PRODUCTLEVEL2 TITLE
; Y' E2 H& |- U! m( ^' _) `' X; K===================================================================================================================================. Z$ e6 K! _7 o5 v, [2 m
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager& f: b0 y. d, d. U6 q. v
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
1 C4 }+ }4 h7 F1 P& l1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license1 O( j: k3 y7 N6 o6 p
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short2 ?5 V3 _. O! }
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system4 E) P6 a: x0 X2 ?8 r
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
* b/ I% H, d. j1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol+ K5 R: ^8 M; r* H: D; i3 g
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file: r# A: Q/ B2 |. f) f: c L
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
* g: x( |$ ^* u: @+ I$ k; r1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'' i) C+ ]$ ?9 z7 d
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .
6 V1 y6 o U; I: r1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
. L3 I9 L/ t, f9 _5 [; X1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
; V9 ]* V' r5 E! B
) t7 F- `) N' n/ I, FDATE: 03-11-2016 HOTFIX VERSION: 067
4 g: c; \' \7 n( y0 w- d===================================================================================================================================+ c1 `2 J; {" R- G' d
CCRID PRODUCT PRODUCTLEVEL2 TITLE, W b- ]0 q; u' o
===================================================================================================================================! e; S* C9 h5 b ^
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
3 Q9 D0 s$ G' I# g# ^1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
?5 L A" \2 ~1 w* F6 }8 F8 r1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error% h$ U0 e! `$ B) s1 G& V: K# l H
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'# M d* ]( [ E. \* P( f) m
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
. A9 ~0 i, Q3 Z/ [1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net' O0 D. J- L& k( d5 M/ K: c
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file, ]7 [# ~; B- o
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes% L) {& Q- e1 c% A
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
6 G2 r: J3 o9 Z6 h$ Z1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
" v9 s# `. J1 l9 }: ?, X1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
) B* s0 \% `* @1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
. x& g" _* N. v3 H& |% w1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer: x/ K A% V& b& E+ e, Z3 l2 T5 T# O
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
. D+ V6 j& C; \! f2 v5 q1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform: ?" H4 P5 ]2 q
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
! ]+ Q3 n# S2 q- B4 l; X1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
. E1 M) d* i' O: N! ^1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.5 C( q( {! R4 m. }, n
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
! J) C% g6 b z6 ]1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines* Y7 q' l7 ~3 S5 A% \
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols. R& |0 g2 m% y0 `
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board, r- N( S" e% ^ q7 e6 ?, J& D! M
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
1 y( {0 V' A1 M5 y, e' @) h1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash! h3 f: m; H- p a7 o$ V1 ?
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked8 D) |, O& c4 K) C* T
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
8 c& ~% R6 q4 |" d% @! \1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
; A; v2 c8 e+ ]# c1 ^/ [1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design t9 x- M9 \" h1 U! ~
- Z4 b- b# U" r' |2 f2 b' s
DATE: 02-26-2016 HOTFIX VERSION: 066) X; x: V( L) t( L$ [
===================================================================================================================================
8 m5 c5 i, U3 CCCRID PRODUCT PRODUCTLEVEL2 TITLE
! p; M3 f& \% X===================================================================================================================================
3 X5 ?* R' F) o& h( ?' p/ L/ _, x1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
0 n7 L( n) r. Y) R1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes" X! D: Y) N; N* C7 ^- u
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
/ G* P9 m, A7 I! ~0 B! z) w6 Y1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message- d2 S. Y$ m8 s' ~$ x
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr5 Q: I* r# d4 I1 Q9 I9 D8 r. X
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue9 c; e3 A+ S) I; G" m
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
- n8 S) G% b3 ~5 Z1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
4 z s7 D# c8 y) p2 a3 f% s3 t% \: V1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run
& e3 r* s$ F( f, k) x9 S1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed3 O- s k' F1 u& p1 q7 f
a# C9 ?. ]$ J
DATE: 02-12-2016 HOTFIX VERSION: 065
# n) @ \4 ]5 O( q1 S) a5 a) d1 W===================================================================================================================================& b" i) [" E% y. F# Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE; P; p! ^! v, t' Q f. j
===================================================================================================================================
! y! I4 @, _; O7 g# F1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working# y) W8 o% F$ f& ^
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via* V1 Q0 y9 c1 V& K$ d
1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit% B" e2 N/ A" T+ w1 f% _$ j
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
5 l2 O! b& _( N3 b1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
9 H' d. E5 N" I1 o1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
3 V* H8 w: I$ n0 @7 M1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger0 _* h) T' x: c0 V# @, D) `4 s! K
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
* c5 M4 b+ P0 f9 ^% B1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup6 R7 A/ b+ S# N3 |) V, Y
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license. c! e1 |: `' l% Z$ ?
+ e, ^* |9 X) B6 e
DATE: 01-29-2016 HOTFIX VERSION: 064" @: Z" e% i( R- I2 V d2 i0 f
=================================================================================================================================== \3 F, K6 \8 R+ }0 s' o& n
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 g! v$ D) f" v
===================================================================================================================================
8 z1 D0 M7 g) w* m o* h7 o1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
' H) j& o) ]3 J1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF
4 T* ^" i* O- |; h3 ]1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.% u2 ]8 g0 b- e, J5 o. q
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected
2 h, D$ r" K- Y# ?$ g5 ]1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.0 T8 U8 L: K% B. z3 n5 n
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default( `3 s2 T0 |6 [$ W) J. w
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas8 {( d% u4 ]! D- H, {- z
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net4 j1 f1 p! m+ u5 m# G
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
* M' ]; J. o# V6 ?1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic# S8 m6 `. Q8 E# I) Z, S
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor. B2 V& i+ K& V
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)+ t) v( K/ f- G) Q; I. T
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design6 ?2 K# \0 X, q: g* a
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
( r3 M3 v2 {& x3 X9 y3 ?3 j' S1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
6 i! v* D' ~2 M$ L; r( {& L1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
; N2 [; }) A: ^" r" e* x- O1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
8 q4 z `! n" O" O4 @# n% F3 h0 S1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
% v1 C! u. N6 M1 \. i& |1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
8 O3 O9 ~( H8 l. o
5 _4 ]1 n# b$ W& b/ sDATE: 01-15-2016 HOTFIX VERSION: 063
+ o5 K. K. k1 n/ F1 d& L+ F===================================================================================================================================7 G$ H" E- {6 _+ a% @
CCRID PRODUCT PRODUCTLEVEL2 TITLE( z- T1 }5 K" {$ D8 m1 [. C
===================================================================================================================================3 ?4 t; a2 F- r; O
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
: \+ }+ [2 j( `# g* X) b# Z1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
" l1 {5 p2 R5 d1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs; F5 u: V( J" }; k
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
$ s/ _3 u, {3 x: o3 G' f) }: x1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork6 o6 L3 B9 D/ \( e G7 L. K' w
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6& @1 b8 ]( Q% j
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
- d* P9 s8 R: ]4 ^3 E( C* v1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
! I O3 v- X5 i, n3 i1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.
/ e5 Y, V" P) x- S7 ? _5 {1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out) {- [ E8 E7 o" _- \. D- J2 _
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
, T, r4 n2 c9 l1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property) w [) g$ ~1 W8 N/ l5 M, y0 A
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly% w/ v4 x/ o% x7 N, Q; a
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
6 I7 ]' s2 e' U. k' R! V6 O; R1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
+ w) p$ ~0 h9 [+ I' ]1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
9 m) Q ~: T. Q0 Z3 O1 ?: d1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
+ @0 C! \2 w' C! x3 c& ]1519518 CONCEPT_HDL OTHER Genview does not generate split symbols" C0 O2 \5 K' T3 G/ s
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas7 P& g3 ^# |1 Z' K% r" f, Y; a u: z
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports% @* G# K; _% z
1 m4 {* {5 g( @# W. l7 G( iDATE: 12-11-2015 HOTFIX VERSION: 062* g% r$ T) h$ o
===================================================================================================================================
4 u& g" J( c: ^! yCCRID PRODUCT PRODUCTLEVEL2 TITLE
0 G$ x2 _+ U. y8 \===================================================================================================================================7 v6 I" k5 E8 M- |3 j/ r: Y
1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
) ~4 v4 H& _: H1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file+ T& H" l- J, y, t2 [! b- Q% o
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option3 J. k) S" n' l& f) `
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
3 d, I3 j* }1 i& S0 H5 l1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view: J: P; X3 g! P9 w
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
% A" D' j; U7 M" b2 L" m+ K1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
0 c' \* W; v" ]6 P# u! A1 e1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
3 A( l: U' o L. ~$ B1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
* g/ i h9 E4 R, C2 u5 ^1490311 SCM OTHER Block Packaging reports duplication when it should not j2 G5 Q5 n4 N# O7 k
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
, j2 h8 g+ i4 K, t8 m1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
3 W9 l( y# V; A) n1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
# n7 U8 a! Y# {- t) w1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
) h& R7 C0 k ]1 L& C1 B$ x# |* q4 F1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
9 ^: M6 F/ r5 G; s# j7 e1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
6 }% `" V* k7 {; G4 k& `3 s8 G1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types
# D7 m4 P' P: H0 d- e3 t1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'& x D& V4 s% }7 K! C+ n
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly
6 h/ g; p' ^5 L& B1 V1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this- h: Y# P5 v" C* Q6 F
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch9 [% D, _2 H, T2 w
1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
5 ^+ c. q/ R! b+ d1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
% N) L3 C1 R9 r" Z1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks; z" u7 h, r* H: C$ Y
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out$ f0 W7 Z/ O0 O, Y2 z; F+ m; N0 I
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
/ a6 ]6 ?$ e: V0 \8 l! @/ G1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form" p0 c* j+ `- ~: Z4 Y
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
# J/ z9 k! c2 |' {. y1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings b3 C4 C2 S$ ^) x2 R
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location" S; g6 |3 I5 Y1 H. H. Z- r6 y6 _
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized- h/ z% v! g/ Y
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
5 D( B6 @, Z5 |. {' X1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items1 a5 D- }: m* v9 ?) G$ Z
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin% ?' A) ?; k1 S ^
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
. `$ b) L) q# Y1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None! I- E3 a! ]0 ~: Q/ e- O) s
]1 U" c& T1 W# w
DATE: 11-20-2015 HOTFIX VERSION: 061
/ X% r: c4 m+ ?* t===================================================================================================================================; t% v7 o1 a7 t- H' [, r9 M
CCRID PRODUCT PRODUCTLEVEL2 TITLE, F; n b- [9 K% @
===================================================================================================================================& |( H7 {1 w4 ~
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value% K) ?4 i5 o, b
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
$ \* P7 E$ m+ I, S1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only ~2 J+ K9 a; e( t1 b
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
/ l+ `+ g4 q- K9 h& p1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins# }+ u6 P3 z$ q* a/ f# ]
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set9 w0 s: e2 b6 f
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin/ o2 l* A) ^; E
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
. S. H$ r6 M5 n: l, |" J' Q% Z1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
3 A- T; k! i: V( g- w; ^2 k1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets! c( z) l) R( j
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
- r/ E- ?# V) ?, A3 r' u3 V8 Q9 U1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
) k6 v7 d n+ [( k1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable# t: q' y4 q4 d6 ]* o/ p
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
- B& @) E: x {. I1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice# |% s2 }7 k0 Y; {- R* N
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues) [( I+ k- h* w1 k, l
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
0 f: [0 i3 A" X/ D: s2 `2 L1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project) s V# r5 k5 Y( a' o$ m0 J
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.0 O2 t: a( K% i! E9 |
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
: T3 o; R+ r. }: S1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
' `; O- P1 o: l7 x" X9 l2 y1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
+ V# [3 Y- h o5 V( Y6 \1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
- ~- a8 Z1 Y( g, Y' ~1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
* B' [+ l, y" e. P3 L1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
4 t5 G/ @6 H: c5 _: b" }1490299 SCM OTHER ASA does not update revision properly
, Y: j0 X l) I, L {" {: |1 G( y% o1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer: I2 E/ r G& W! I7 W# n
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
z i! R5 I3 b3 w8 k1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working" T4 {/ y% ^8 E, g3 L' T
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong/ }* r. m/ W. s# }
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
% D% \8 }% ~$ P3 b3 h/ x9 W1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
. l) y5 F$ i( o1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
' f6 p, K2 N' B1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size3 \' u. p. P, j7 A/ X" }/ X
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
% C* m9 F, P' B3 r6 Y+ ]' l5 O6 f$ |1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file3 |( H* Q: V$ U5 U5 ~
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
|
/1 
发表于 2016-6-29 12:21
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
发表于 2016-8-17 13:05
