这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？

, F  N+ ~- |4 C( F8 T$ kIf the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
, h# p: g. Q) J1 r: Kassertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
  X/ J# O* K" Y4 c7 ?/ Z3 ]output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
8 m# h4 _& ^: n$ B( T; s1 f) k7 rAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
due to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
4 S  Z" q, i/ f4 _. b$ _$ preset glitches. If this is a real problem in a system, then one might think that using synchronous
resets is the solution. A different but similar problem exists for synchronous resets if these
; ~0 \! ?4 T, {( _1 `, K( T  cspurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
: C( n' Y9 W: z, |true of any data input that violates setup requirements).