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破解SPB16.5成功!
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- Cadence License Server restarted successfully with the new license file 'K:\Cadence\LicenseManager\license.dat'.6 @0 ~+ I2 [! w0 M4 {, a# T8 J) F$ x
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- The new license server setting '5280@3C68B4367E914FC' was successfully added to your CDS_LIC_FILE license path environment variable.. [: `& D+ M. h, o0 k4 q3 J% I
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4 P* Y7 U& T5 ?==============================================================================
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22:01:30 (lmgrd) -----------------------------------------------
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4 ], F* A4 \% d* P1 O22:01:30 (lmgrd) Please Note:
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' J; U! J/ V% \6 L2 \" B: T- ?22:01:30 (lmgrd) This log is intended for debug purposes only. n& a. ^' d( I1 N+ R! E
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22:01:30 (lmgrd) In order to capture accurate license
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22:01:30 (lmgrd) usage data into an organized repository,
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22:01:30 (lmgrd) please enable report logging. Use Flexera Software, Inc.'s# {$ g/ H+ F/ ? ]9 o9 B
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22:01:30 (lmgrd) software license administration solution,/ h; }: Q: q7 i. L0 H( R
4 [( H5 q- b# ~% a* n% P! A22:01:30 (lmgrd) FLEXnet Manager, to readily gain visibility3 N- N- B5 a9 b3 e5 G
' B; i$ B6 k& n/ s22:01:30 (lmgrd) into license usage data and to create8 [, R! z1 L* g7 [8 O* R: Z9 H T
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22:01:30 (lmgrd) insightful reports on critical information like- C7 R* O/ K8 f" }! p" |: l
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22:01:30 (lmgrd) license availability and usage. FLEXnet Manager* j: U% N1 r5 b6 k" B1 Z! b2 k
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22:01:30 (lmgrd) can be fully automated to run these reports on, n: U! [ }7 i8 @! _
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22:01:30 (lmgrd) schedule and can be used to track license
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22:01:30 (lmgrd) servers and usage across a heterogeneous
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22:01:30 (lmgrd) network of servers including Windows NT, Linux
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22:01:30 (lmgrd) and UNIX. Contact Flexera Software, Inc. at
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22:01:30 (lmgrd) www.flexerasoftware.com for more details on how to
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K. l6 Y9 |5 Z3 C/ b22:01:30 (lmgrd) obtain an evaluation copy of FLEXnet Manager& u. ^5 i' k L7 g! D
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22:01:30 (lmgrd) for your enterprise.
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22:01:30 (lmgrd) Done rereading
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22:01:30 (lmgrd) FLEXnet Licensing (v11.9.1.0 build 89952 i86_n3) started on 3C68B4367E914FC (IBM PC) (5/30/2011)
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. i6 ~4 v) ~; ?* u$ [/ e$ f22:01:30 (lmgrd) Copyright (c) 1988-2010 Flexera Software, Inc. All Rights Reserved.
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22:01:30 (lmgrd) US Patents 5,390,297 and 5,671,412.7 M/ L2 n, q& |6 h2 M" `
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22:01:30 (lmgrd) World Wide Web: http://www.flexerasoftware.com
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( a* D Y" |* K- \4 y0 {# [; w22:01:30 (lmgrd) License file(s): K:\Cadence\LicenseManager\license.dat
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22:01:30 (lmgrd) Starting vendor daemons ...
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22:01:31 (cdslmd) WARNING Set environment variable cdslmd_ENH_RECORDS=1 to enable ENH records usage logging enhancements
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22:01:33 (cdslmd) Using options file: ".exe"
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22:01:37 (cdslmd) ABIT ALL_EBD AMD_MACH
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22:01:37 (cdslmd) Affirma_model_checker Affirma_model_packager_export Affirma_sim_analysis_env % q9 n: i9 x% E& K7 I% s# r
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22:01:37 (cdslmd) Allegro_CAD_Interface Allegro_Design_Editor_620 Allegro_Designer 8 e) Q% Z4 u% d
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22:01:37 (cdslmd) Allegro_PCBSI_SParams Allegro_PCBSI_SerialLink Allegro_PCB_Design_230
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22:01:37 (cdslmd) Allegro_PCB_Design_620 Allegro_PCB_Design_GXL Allegro_PCB_Design_Planner 4 b6 a, _* w. O* Q
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22:01:37 (cdslmd) Allegro_PCB_Editor_GXL Allegro_PCB_Global_Route_Env Allegro_PCB_Intercon_Feas - Y/ \- q' p$ b C
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22:01:37 (cdslmd) Allegro_PCB_RF Allegro_PCB_Router_210 Allegro_PCB_Router_230 ! O2 u5 F1 K5 e4 n
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22:01:37 (cdslmd) Allegro_PCB_SI_630 Allegro_PCB_SI_630_Suite Allegro_Package_620
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22:01:37 (cdslmd) Assura_LVS Assura_MP Assura_OPC
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22:01:37 (cdslmd) Atmel_ATV Attsim_option_ATS Base_Digital_Body_Lib 0 |- B7 e5 \7 _0 g5 F+ O' q
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22:01:37 (cdslmd) BuildGates CELL3 CELL3_ARO
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22:01:37 (cdslmd) Cadence_chip_assembly_router Capture CaptureCIS
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22:01:37 (cdslmd) Cierto_SPW_multimedia_kit Cierto_SPW_pcscdma_VE Cierto_Wireless_LAN_Library
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22:01:37 (cdslmd) ConcICe_Option Concept-HDL ConceptHDL + C+ t. p) I, U/ g; P
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2 a. r8 D% {7 i5 p3 b7 t22:01:37 (cdslmd) DPcongest DPdelayCalc DPecoIpo * |! A: B" _- s( m0 }8 m
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22:01:37 (cdslmd) DPhyperPlaceCell DPhyperPlaceGarray DPparasitic 9 y# @# A# E- {! d
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22:01:37 (cdslmd) DPpearlLocked DPqplaceAB DPqplaceGA ! D/ B2 g; ^* r& N" r0 V
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22:01:37 (cdslmd) DPsynopsys DPunivInterface DPwplaceLocked 0 D: w2 T5 e8 e* [& i6 {1 _
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22:01:37 (cdslmd) DRAC2CORE DRAC2DRC DRAC2LVS + r# J7 J/ v7 k* f: \
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22:01:37 (cdslmd) DRACACCESS DRACDIST DRACERC
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22:01:37 (cdslmd) DRACLPE DRACLVS DRACPG_E
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22:01:37 (cdslmd) DRACPLOT DRACPRE DRACSLAVE
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22:01:37 (cdslmd) Datapath_Preview_Option Datapath_VHDL Datapath_Verilog : p4 k& o7 \6 ~: G0 m' K8 L
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' a# n: F X! b$ w" R( \# v22:01:37 (cdslmd) EBD_edit EBD_floorplan EBD_power + S3 q/ Z, E: ] Q
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22:01:37 (cdslmd) EDIF_Netlist_Interface EDIF_Schematic_Interface EMCdisplay
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1 h. K6 w2 u. s8 O2 C" P0 b22:01:37 (cdslmd) EMControl EMControl_Float EditBase_ALL ' S9 Y! d# ^& _& |7 A2 z
# Q: X6 M; V; u" E22:01:37 (cdslmd) EditFST_ALL Envisia_DP_SI_design_planner Envisia_Datapath_option
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22:01:37 (cdslmd) Envisia_GE_ultra_place_route Envisia_LowPower_option Envisia_PKS
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22:01:37 (cdslmd) Envisia_SE_SI_place_route Envisia_SE_ultra_place_route Envisia_Utility
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22:01:37 (cdslmd) Envisia_synthesis_with_PKS Extended_Digital_Body_Lib Extended_Digital_Lib
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22:01:37 (cdslmd) Extended_Verilog_Lib FPGA_Flows FPGA_Tools ! y0 W2 y" i; i+ R: C5 h8 o d
. I; U! v ^8 C0 {/ T22:01:37 (cdslmd) FUNCTION_LIB Framework GATEENSEMBLE " H( i5 z/ Y8 L g" k
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22:01:37 (cdslmd) GATEENSEMBLE_ARO GATEENSEMBLE_CROSSTALK GATEENSEMBLE_CTS & e9 H0 ^ E. g" R; A) l
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22:01:37 (cdslmd) GATEENSEMBLE_CTS_LE GATEENSEMBLE_CTS_UL GATEENSEMBLE_ECL
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8 c, H, b6 N$ {. U1 \( }22:01:37 (cdslmd) GATEENSEMBLE_PA GATEENSEMBLE_PR_LE GATEENSEMBLE_PR_UL
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22:01:37 (cdslmd) GATEENSEMBLE_QPLACE_TIMING GATEENSEMBLE_SCAN GATEENSEMBLE_TIMING
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22:01:37 (cdslmd) GATEENSEMBLE_TIMING_LE GATEENSEMBLE_TIMING_UL GATEENSEMBLE_UNLIMITED
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22:01:37 (cdslmd) Intrica_powerplane_builder LAS_Cell_Optimization LDPbaseCell ( B' ^4 l* c7 a$ b9 s! S5 h
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22:01:37 (cdslmd) LDPbaseGarray LDPclock LDPhyperPlaceCell & m. }6 O. P' e# R
7 ~' X9 e% ]8 H6 U) v22:01:37 (cdslmd) LDPhyperPlaceGarray LEAFPROG-SYS LEAPFROG-BV
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- j" ~0 S: W' z" ?! t7 Z% }22:01:37 (cdslmd) LID10 LID11 LINAR_LIB : q4 F/ }" x9 q
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22:01:37 (cdslmd) Layout LayoutEE LayoutEngEd + p- N; ?8 w+ h( N1 A9 J, n
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22:01:37 (cdslmd) MTI_option_Attsim Model_Check_Analysis NC_VHDL_Simulator
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22:01:37 (cdslmd) NC_Verilog_Data_Prep_Compiler NC_Verilog_Simulator Nihongoconcept * w8 b Q( d8 i
# H* Q5 {; A5 K+ g% b% m0 a/ ^22:01:37 (cdslmd) OASIS_Simulation_Interface OpenModeler OpenModeler_SFI
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- r; o* P3 j3 O22:01:37 (cdslmd) OpenModeler_SWIFT OpenSim OpenWaves
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. h! {/ g7 }5 r9 ^7 c- w& i22:01:37 (cdslmd) Optimizer OrCAD_Capture_CIS_option OrCAD_EE_Designer_Plus
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22:01:37 (cdslmd) OrCAD_PCB_Designer OrCAD_PCB_Designer_Basics OrCAD_PCB_Designer_PSpice - R# H% B/ Q+ ]6 l1 e) l0 U3 i1 K
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22:01:37 (cdslmd) OrCAD_PCB_Editor OrCAD_PCB_Editor_Basics OrCAD_PCB_Router 1 ]7 I; Z- ^, _" \+ a% `5 x
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22:01:37 (cdslmd) OrCAD_Signal_Explorer OrCAD_Unison_EE OrCAD_Unison_PCB # {! j' N8 Y; K/ n3 }1 \
v# l( J3 w7 W8 N! S) q. Q: ^( A22:01:37 (cdslmd) OrCAD_Unison_Ultra PCB_Design_studio PCB_design_expert ; L$ q# E$ v1 V2 V
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22:01:37 (cdslmd) PCB_designer PCB_librarian_expert PCB_studio_variants : x7 a) E h; t# g" |3 x- ^
7 H6 j) M+ T/ C( q22:01:37 (cdslmd) PE_Librarian PICDesigner PIC_Utilities
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1 n4 _1 h2 N, N) @1 a6 t2 E( _6 B22:01:37 (cdslmd) PLD PPR-HPPA PPRoute_ALL 0 l# A; Y0 ?6 b; W! a
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( b2 X$ m3 ^% N22:01:37 (cdslmd) PSpiceAAStudio PSpiceAD PSpiceBasics 9 N o' w7 }) @" Q
2 c/ z. c1 F. X7 E1 E* v22:01:37 (cdslmd) PSpiceOPTIOpt PSpiceOptimizer PSpicePerfOpt
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6 q; c- ^# o" g) W# H/ |. F, N! _22:01:37 (cdslmd) Pearl_Cell PlaceBase_ALL Placement_Based_Optimization ; l% I- G( |5 M
; F, H. @4 e3 A22:01:37 (cdslmd) Placement_Based_Synthesis PowerIntegrity Prevail_Board_Designer
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22:01:37 (cdslmd) Prevail_Correct_By_Design Prevail_Designer Preview_Synopsys_Interface , P; q( }% K* i$ n
" f7 w; x, g+ _% U5 [22:01:37 (cdslmd) PspiceADBasics QPlace Quickturn_Model_Manager
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, ?/ ]2 \0 S- A8 r5 T22:01:37 (cdslmd) RB_6SUPUC_ALL RapidPART RouteADV_ALL
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22:01:37 (cdslmd) RouteBase RouteBase_ALL RouteDFM_ALL $ b g- J ^! |6 S) H2 ?3 G6 Q
- P1 `( x; D2 a' T0 ]22:01:37 (cdslmd) RouteFST_ALL RouteHYB_ALL RouteMVIA_ALL 9 E1 \0 C8 r0 P# T
/ p k M0 e. P# E9 Z0 k- T22:01:37 (cdslmd) SDT_MODEL_MANAGER SPECCTRAQuest SPECCTRAQuest_EE
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22:01:37 (cdslmd) SPECCTRAQuest_EE_SI SPECCTRAQuest_Planner SPECCTRAQuest_SI_expert
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22:01:37 (cdslmd) SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer SPECCTRA_256U % F/ N/ `7 h: M6 b
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22:01:37 (cdslmd) SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD , y, v, T4 Y7 C# p
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2 {4 I/ i$ \1 K3 L ?4 a22:01:37 (cdslmd) SPECCTRA_QE SPECCTRA_Unison_PCB SPECCTRA_Unison_Ultra & p$ }8 A$ a( a# l5 i
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22:01:37 (cdslmd) SPECCTRA_VT SPECCTRA_autoroute SPECCTRA_expert
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22:01:37 (cdslmd) SPECCTRA_expert_system SPECCTRA_performance SPW_BDE & u- V/ x9 z- Z
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22:01:37 (cdslmd) SPW_BER_Sim SPW_BVHDL_CDMA_LIB SPW_BVHDL_COMM_FXP 2 [' Z# }/ ] z) ], {
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22:01:37 (cdslmd) SPW_CGS_ANY SPW_CGS_C30 SPW_CGS_C40
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22:01:37 (cdslmd) SPW_CGS_DSP32C SPW_CGS_M96002 SPW_CGS_PKB 3 L+ X" K/ E% ^+ J- V0 j3 _
# o- I4 r$ P+ H" W+ D; c22:01:37 (cdslmd) SPW_CGS_STANDARD_C SPW_COSIM_LEAPFROG SPW_COSIM_VERILOG_XL - g7 }5 c" V& |# p u
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22:01:37 (cdslmd) SPW_FDS SPW_FMG SPW_FSM
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22:01:37 (cdslmd) SPW_HDS_VHDL_LINK SPW_HLS SPW_LIB_CDMA_LIB 7 u! `6 Y! b( `
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22:01:37 (cdslmd) SPW_LIB_DSP563S SPW_LIB_DSP566S SPW_LIB_DSP568S " l! G8 X( k$ s1 q; l) m
( {% C( W" w# _' B" G6 r( v22:01:37 (cdslmd) SPW_LIB_DSPGROUP SPW_LIB_GSM_LIB SPW_LIB_HDS_ARC - }; p/ G) \4 b2 a
8 n8 c6 I1 t# ]4 f0 n( T! C2 D8 d22:01:37 (cdslmd) SPW_LIB_HDS_ISL SPW_LIB_HDS_LIB SPW_LIB_HDS_MAIN A+ u& ~5 u! F F+ u4 ?0 p, a
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22:01:37 (cdslmd) SPW_LIB_HDS_MICRO SPW_LIB_IS136LIB SPW_LIB_IS95LIB
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22:01:37 (cdslmd) SPW_LIB_ISL SPW_LIB_M5630X SPW_LIB_MATLAB
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5 G: ^' y) [1 v, h. ]; K; A22:01:37 (cdslmd) SPW_LIB_SGSTHOMSON SPW_LIB_TIC54X SPW_LIB_TIC5X
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# k0 o& ?6 r7 n' y: q% z* N( [: w22:01:37 (cdslmd) SPW_LIB_VFL SPW_LINK_VERILOG SPW_LINK_VHDL
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* G' y1 l( G% E% J0 y$ A22:01:37 (cdslmd) SPW_LINK_VHDL_BEH SPW_LSF_Link SPW_MODEL_MANAGER
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0 S4 F# r2 H% J( G5 s' l! W22:01:37 (cdslmd) SPW_MPX SPW_SIGCALC SPW_SIM
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22:01:37 (cdslmd) SPW_SIM_UI SPW_Smart_Antenna_Library SQ_Digital_Logic_SI_Lib
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22:01:37 (cdslmd) SQ_FPGA_SI_Lib SQ_Memory_SI_Lib SQ_Microprocessor_SI_Lib 4 E3 z! _( F2 L5 D4 R
0 [, n1 v$ r0 T9 R22:01:37 (cdslmd) SQ_ModelIntegrity SWIFT Schematic_Generator
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! A$ _' u/ a1 T: m5 l22:01:37 (cdslmd) SiP_Digital_Architect_GXL SiP_Digital_Architect_GXL_II SiP_Digital_Architect_XL * g3 R& Z; p( I/ L/ @" m9 R: F
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22:01:37 (cdslmd) SiP_Digital_Layout_GXL SiP_Digital_SI_XL SiP_Digital_SI_XL_II
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3 L# U* ?$ E( E/ D* X22:01:37 (cdslmd) SiP_RF_Architect SiP_RF_Architect_XL SiP_RF_Layout_GXL
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22:01:37 (cdslmd) SigNoiseEngineer SigNoiseExpert SigNoiseStdDigLib
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22:01:37 (cdslmd) SigNoise_Float SiliconQuest Silicon_Ensemble
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22:01:37 (cdslmd) Silicon_Ensemble_CTS Silicon_Ensemble_DSM Silicon_Ensemble_DSM_Crosstalk
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5 [! M8 f" m' ~4 w2 L, |22:01:37 (cdslmd) Silicon_Ensemble_OpenDev Silicon_Ensemble_OpenExe Silicon_Synthesis_QPBS ) f' c$ d, C1 d" z+ K/ m& K
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22:01:37 (cdslmd) SimVision SpectreBasic SpectreRF + k7 D a f% A
b& {' V* q# r4 r) E% {22:01:37 (cdslmd) Spectre_BTAHVMOS_Models Spectre_BTASOI_Models Spectre_NorTel_Models + n1 c7 a8 o/ H$ h
; A# u8 N% U: _/ h) J22:01:37 (cdslmd) Spectre_ST_Models Substrate_Coupling_Analysis Synlink_Interface
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3 J0 J3 W- G- R1 I- c5 b22:01:37 (cdslmd) TOPOLOGY_EDITOR Trans_level_option_Attsim UET 3 ]$ _5 C) t; n" V& N6 {
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22:01:37 (cdslmd) UNISON_SPECCTRA_6U Unison_SPECCTRA_4U Universal_Smartpath : n. }6 U8 h" o- r* p' G
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22:01:37 (cdslmd) VB_6SUPUC_ALL VCC_Editors VCC_SW_Estimator $ k$ ?+ I! e: K4 t% I$ |' S
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22:01:37 (cdslmd) VCC_Simulators VCC_links_to_implementation VERILOG-SLAVE 1 N- ], v% J- \" d5 f# F0 A
8 e/ b! B1 Z5 F6 e$ u22:01:37 (cdslmd) VERILOG-XL VERITIME VERLOG-SLAVE
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22:01:37 (cdslmd) VHDLLink VITAL-XL VXL-ALPHA ! G) P3 ^5 |3 M6 B
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22:01:37 (cdslmd) VXL-LMC-HW-IF VXL-SWITCH-RC VXL-TURBO
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22:01:37 (cdslmd) Vampire_MP Vampire_RCX Vampire_UI
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22:01:37 (cdslmd) Verif_Ckpit_Analysis_Env Verif_Ckpit_Runtime_Env ViewBase
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22:01:37 (cdslmd) ViewBase_ALL Virtuoso_Core_Characterizer Virtuoso_Core_Optimizer $ M1 M% ~6 i2 c$ ^' L) t
' F" u. T6 W6 j9 l1 }- p, C22:01:37 (cdslmd) Virtuoso_Schem_Option Virtuoso_SiI Virtuoso_Turbo
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22:01:37 (cdslmd) Virtuoso_XL Virtuoso_custom_placer Virtuoso_custom_router
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22:01:37 (cdslmd) XBLOX-HPPA XDE-HPPA _21900 ; p& T* m! z* g1 `' @* ]5 c+ |& U
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22:01:37 (cdslmd) a2dxf actomd adv_package_designer
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22:01:37 (cdslmd) adv_package_designer_expert adv_package_engineer_expert allegro_dfa 1 w" f$ v1 h2 A4 F s
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22:01:37 (cdslmd) allegro_dfa_att allegro_non_partner allegroprance % J1 n4 h% U# C9 T) n' B
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22:01:37 (cdslmd) apd1 archiver arouter 0 i9 o/ C' @( u& G- z
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22:01:37 (cdslmd) caeviews cals_out cbds_in
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22:01:37 (cdslmd) cdxe_in comp concept 8 ~. F3 N2 w2 E0 w6 O9 p1 n: G
9 \$ ^/ c0 m9 c1 {2 y5 P! C22:01:37 (cdslmd) conceptXPC coverscan-analysis coverscan-recorder 8 y7 I4 f+ P' g2 X& U
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22:01:37 (cdslmd) cpe cpte crefer
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22:01:37 (cdslmd) cvtomd debug dfsverifault 5 }1 M. a0 ?; @, `. M; z
9 D: x F9 M u1 n: R U5 \22:01:37 (cdslmd) dracula_in dxf2a e2v
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22:01:37 (cdslmd) eCapture edif-HPPA edif2ged
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. u( c' j7 Y. [) q: {22:01:37 (cdslmd) expgen fcengine fcheck
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22:01:37 (cdslmd) fethman fetsetup gbom / c- J6 l+ C" @: a2 K0 B8 y
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22:01:37 (cdslmd) ged2edif gilbert glib
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# b* U& O/ }& @/ v+ R22:01:37 (cdslmd) gloss gphysdly gscald 4 P/ [; o/ @% R
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22:01:37 (cdslmd) gspares hp3070 hyperExtract
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7 ?" f0 M2 F. m& E* ^22:01:37 (cdslmd) hyperRules iges_electrical intrgloss + o" Y' |+ d9 F2 V
5 W, @, g0 k' g3 p8 y22:01:37 (cdslmd) intrroute intrsignoise ipc_in & B* x. ^( v" N6 f* D: X
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22:01:37 (cdslmd) ipc_out libcompile lwb 6 q4 ]7 Z" S9 L. ?8 k* c1 v
% u6 n. H& d; o, w6 U22:01:37 (cdslmd) mdin mdout mdtoac ) M) U8 Z5 s2 u7 t+ `
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22:01:37 (cdslmd) mdtocv multiwire odan
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8 ]4 h3 U+ O; K N22:01:37 (cdslmd) packager partner pcb_cursor
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22:01:37 (cdslmd) pcb_editor pcb_engineer pcb_interactive * x: E% |! C2 K3 f+ x5 Q0 M) _
" h6 [ Y2 ^+ w; y0 i) n22:01:37 (cdslmd) pcb_prep pcb_review pcomp
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22:01:37 (cdslmd) pillar.abstract pillar.areaPdp pillar.areaPlanner N; Z. {6 t+ x0 L: ?
! J: Z" f3 x7 H4 O w3 b22:01:37 (cdslmd) pillar.cdsIn pillar.cdsOut pillar.cellPdp
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22:01:37 (cdslmd) pillar.cellPlanner pillar.db pillar.dbdev - p! I8 ~/ O& p$ i
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22:01:37 (cdslmd) pillar.dbperl pillar.defIn pillar.defOut 4 d8 r. ?, K! G' h. s- W: O
/ q' C& r8 u/ M; U$ k22:01:37 (cdslmd) pillar.dpdev pillar.dpuxIn pillar.dpuxOut
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. i& J) l" t n+ _22:01:37 (cdslmd) pillar.edifIn pillar.edifOut pillar.gatePdp - @% F2 ~" ]% @( g/ K
/ j- j3 k/ |+ j8 }, J8 ^22:01:37 (cdslmd) pillar.gatePlanner pillar.gdsIn pillar.gdsOut
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22:01:37 (cdslmd) pillar.ge pillar.gui pillar.ldexpand / G- {" c5 n) y% s
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22:01:37 (cdslmd) pillar.lefIn pillar.lefOut pillar.pdp
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22:01:37 (cdslmd) pillar.verIn pillar.verOut pillar.vhdlIn 6 ]" N8 C+ G' h. l: F
3 W! R4 n& f+ x# s" C22:01:37 (cdslmd) pillar.vhdlOut pillar.vre pillar.xl 8 A- M$ q: u: p5 h% q) }
0 t" Z% Z2 W+ D. T! c# W22:01:37 (cdslmd) pillar.xlcm pillar.xldev placement 4 r/ B9 X& g6 R+ L4 k! I1 j! G
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22:01:37 (cdslmd) plotVersa ptc_in ptc_out # Q: P5 ?2 Y+ K) u
9 w1 p2 X6 [" J22:01:37 (cdslmd) quanticout rapidsim realchiplm
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' a4 }+ d( J) R$ u22:01:37 (cdslmd) redifnet rt sdrc_in " z& I5 Q" K; y
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22:01:37 (cdslmd) sdrc_out shapefill sigxp 8 f; K! _% k8 R3 F% {
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22:01:37 (cdslmd) skillDev sqpkg stream_in . j/ K6 H; R0 V7 ~( e g6 R0 T6 [/ c
2 h' v) ~9 I7 R7 B9 f22:01:37 (cdslmd) stream_out swap sx
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/ T; l8 U) n8 Q22:01:37 (cdslmd) synSmartIF synSmartLib synTiOpt
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' E, Y8 T2 L( D22:01:37 (cdslmd) tsTSynVHDL tsTSynVLOG tsTestGen ; Y* x4 ]4 t' }" J3 t$ W. |: m
1 z( N1 l" c: w0 W0 |% O22:01:37 (cdslmd) tsTestIntf tscr.ex tune
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2 r6 h/ \& T4 ?& o! B22:01:37 (cdslmd) tw01 tw02 v2e
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: O5 B; M; Y* y3 L2 Z- ]22:01:37 (cdslmd) verfault verifault vgen ! Z/ Y+ D6 y, w9 q: T/ O( ?$ L
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22:01:37 (cdslmd) viable visula_in vloglink
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% r' ~# w$ A2 w22:01:37 (cdslmd) wedifsch xilCds xilComposerFE 1 p2 J, b2 G% F* I
2 w' o2 E( {: Q+ v1 d+ `22:01:37 (cdslmd) xilConceptFE xilEdif OrCAD_FPGA_System_Planner 5 z: Z) X, H& [- g$ R/ n& N
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22:01:37 (cdslmd) Allegro_FPGA_System_Planner_L Allegro_FPGA_System_Planner_XL Allegro_FPGA_System_Plan_GXL " e' L& J0 p8 \5 s' j
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22:01:37 (cdslmd) Allegro_FPGA_System_2FPGA Allegro_Design_Publisher ) P H! h4 F9 S# ]0 M: ^
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22:01:37 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines
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22:01:37 (cdslmd) 6 {) ^+ o! O% o
0 G0 r; i+ ?& H- H9 j22:01:37 (cdslmd) EXTERNAL FILTERS are OFF
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3 O9 Y, ]9 b- g% q$ t22:01:37 (cdslmd) CANNOT OPEN options file ".exe"
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22:01:37 (lmgrd) cdslmd using TCP-port 1228
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6 Z3 {; F. L2 x3 `, t# q22:01:42 (cdslmd) TCP_NODELAY NOT enabled* J' {- o/ h2 L: _1 x! M! f0 y
D8 q5 q; c) ~0 h" \: \22:01:43 (cdslmd) OUT: "100" Administrator@3C68B4367E914FC % ]! K |. @& H$ d! E
2 N/ G' \* A5 _( F& I& w: D22:01:43 (cdslmd) IN: "100" Administrator@3C68B4367E914FC |
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