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破解SPB16.5成功! r) K: [1 n) `( k2 Y
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运行K:\Cadence\LicenseManager\LicenseServerConfiguration.exe 配置程序时,提示如下:5 y+ O8 Z1 g2 ^ o, U
6 `; n( x8 v& o: @. @" `5 ~- Cadence License Server restarted successfully with the new license file 'K:\Cadence\LicenseManager\license.dat'.
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- The new license server setting '5280@3C68B4367E914FC' was successfully added to your CDS_LIC_FILE license path environment variable.1 |' V$ D" j |0 f+ r: n2 s* N. R
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& T! V9 @" O! Y- U; V7 }1 J4 Vdebug.log
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! M% K4 w& ?" | m" M; T. {22:01:30 (lmgrd) Please Note:4 H. ^/ B. r$ s! `; @
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22:01:30 (lmgrd) ) m$ e* Y% x# Z9 \* e* d/ B$ U* C
$ V/ X3 P& B% c+ f l: S8 ]22:01:30 (lmgrd) This log is intended for debug purposes only.1 m( g3 g) N* j; {8 a
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22:01:30 (lmgrd) In order to capture accurate license$ i$ _& y9 [4 ]3 H
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22:01:30 (lmgrd) usage data into an organized repository,5 \$ ~9 R+ ~+ y: y
) k2 A5 U& x* r3 I8 Y0 M22:01:30 (lmgrd) please enable report logging. Use Flexera Software, Inc.'s; q! H7 i" m' l, l
! ?7 G$ e1 p# |) Z# ?/ V+ `# O22:01:30 (lmgrd) software license administration solution,
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* k0 H+ ~5 F4 P0 O8 U22:01:30 (lmgrd) FLEXnet Manager, to readily gain visibility
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" H/ A r% r* H7 {$ M! `22:01:30 (lmgrd) into license usage data and to create
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: k! V- ` H/ i. H3 l2 D22:01:30 (lmgrd) insightful reports on critical information like1 y* x+ f: H% o0 `" R: D! s- _
' T! F6 e5 a0 [8 w, G: j. A22:01:30 (lmgrd) license availability and usage. FLEXnet Manager6 m: m% I' M5 [; h
% Z2 B: I* p3 y+ u% _4 l22:01:30 (lmgrd) can be fully automated to run these reports on
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6 T- _* e) V6 D$ d" W/ ?8 _22:01:30 (lmgrd) schedule and can be used to track license7 k& y- A/ l8 h; K
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22:01:30 (lmgrd) servers and usage across a heterogeneous
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22:01:30 (lmgrd) network of servers including Windows NT, Linux
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22:01:30 (lmgrd) and UNIX. Contact Flexera Software, Inc. at
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3 v% p& u6 Z" x3 ~5 g22:01:30 (lmgrd) www.flexerasoftware.com for more details on how to
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22:01:30 (lmgrd) obtain an evaluation copy of FLEXnet Manager( v6 }) d( V8 Z# Q+ C! o
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( h0 P3 i, m) r4 I Y22:01:30 (lmgrd) Done rereading) J4 v, ]3 r( L8 D8 j
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22:01:30 (lmgrd) FLEXnet Licensing (v11.9.1.0 build 89952 i86_n3) started on 3C68B4367E914FC (IBM PC) (5/30/2011)! p. z4 R/ @6 A7 j
" C- ` g- l9 f' U22:01:30 (lmgrd) Copyright (c) 1988-2010 Flexera Software, Inc. All Rights Reserved.
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22:01:30 (lmgrd) US Patents 5,390,297 and 5,671,412.
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22:01:30 (lmgrd) World Wide Web: http://www.flexerasoftware.com; }4 {; V' [0 K
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22:01:30 (lmgrd) License file(s): K:\Cadence\LicenseManager\license.dat" e- V( n, i' M
( c" G/ M$ J5 q; h0 n22:01:30 (lmgrd) lmgrd tcp-port 5280) |8 O. Q! B; l) \
W' z7 P8 l& w; j' h* b& T% H22:01:30 (lmgrd) Starting vendor daemons ... $ ^9 t {) h5 Y6 V \4 a
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22:01:30 (lmgrd) Started cdslmd (pid 2772)5 W3 R4 L2 F: a, Y* P& e
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22:01:31 (cdslmd) FLEXnet Licensing version v11.9.1.0 build 89952 i86_n3$ W4 Y) }7 X1 Z4 o
7 f+ _% P; a' }& l/ H8 D22:01:31 (cdslmd) WARNING Set environment variable cdslmd_ENH_RECORDS=1 to enable ENH records usage logging enhancements" n( ]* I- o2 t, Z
# B( V, H: \' ~; z, I) n! `22:01:33 (cdslmd) Using options file: ".exe"" z/ e; K8 _6 G0 t$ ~- A3 G
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22:01:37 (cdslmd) Server started on 3C68B4367E914FC for: 100
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4 {, U3 p( u6 k22:01:37 (cdslmd) ABIT ALL_EBD AMD_MACH + [( a4 {& R$ }
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22:01:37 (cdslmd) AMS_environment ANALOG_WORKBENCH APD 1 G0 |# H9 D1 Y/ H
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22:01:37 (cdslmd) AWBSimulator AWB_BEHAVIOR AWB_Batch
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22:01:37 (cdslmd) AWB_MIX AWB_PPLOT AWB_RESOLVE_OPT ; ], W1 d0 [/ m9 |
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y |8 |: N$ w9 ~4 b" Q& [22:01:37 (cdslmd) Affirma_3rdParty_Sim_Interface Affirma_AMS_distrib_processing Affirma_NC_Simulator
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" U8 T2 O! ^! y# D( Q22:01:37 (cdslmd) Affirma_RF_IC_package_modeler Affirma_RF_SPW_model_link Affirma_accel_transistor_sim / C; A X0 l' h j
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22:01:37 (cdslmd) Affirma_advanced_analysis_env Affirma_equiv_checker_prep Affirma_equivalence_checker
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22:01:37 (cdslmd) Affirma_model_checker Affirma_model_packager_export Affirma_sim_analysis_env
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22:01:37 (cdslmd) Affirma_trans_logic_abstracter Allego_design_expert AllegroSLPS * a' m! t7 |: F& c k7 ^
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22:01:37 (cdslmd) Allegro_CAD_Interface Allegro_Design_Editor_620 Allegro_Designer
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2 ~: \1 o6 l. ~! z& E* G22:01:37 (cdslmd) Allegro_Designer_Package_620 Allegro_Expert Allegro_Librarian
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2 d$ {- w: b" g& d5 N22:01:37 (cdslmd) Allegro_PCB Allegro_PCBSI_Backplane Allegro_PCBSI_Performance ; {# ~; [! I0 @) O. {, ]
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22:01:37 (cdslmd) Allegro_PCBSI_SParams Allegro_PCBSI_SerialLink Allegro_PCB_Design_230 6 F/ ^( K1 p" j: `8 W
* O+ B& D7 i9 I1 w- O K, Z6 c! H22:01:37 (cdslmd) Allegro_PCB_Design_620 Allegro_PCB_Design_GXL Allegro_PCB_Design_Planner " |0 {5 k- Y# ?6 O8 k V& c
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22:01:37 (cdslmd) Allegro_PCB_Editor_GXL Allegro_PCB_Global_Route_Env Allegro_PCB_Intercon_Feas
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22:01:37 (cdslmd) Allegro_PCB_Intercon_Flow_Desn Allegro_PCB_Interface Allegro_PCB_Partitioning l2 L* r# w2 k7 H8 k# V2 X
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22:01:37 (cdslmd) Allegro_PCB_RF Allegro_PCB_Router_210 Allegro_PCB_Router_230
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22:01:37 (cdslmd) Allegro_PCB_Router_610 Allegro_PCB_SI_230 Allegro_PCB_SI_620
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22:01:37 (cdslmd) Allegro_PCB_SI_630 Allegro_PCB_SI_630_Suite Allegro_Package_620 1 W' l0 B( S; ?& q( ^
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22:01:37 (cdslmd) Allegro_Package_SI_620_Suite Allegro_Package_SI_L_II Allegro_Packager_Designer_620
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22:01:37 (cdslmd) Allegro_Performance Allegro_Pkg_Designer_620 Allegro_Pkg_Designer_620_Suite
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22:01:37 (cdslmd) Allegro_Symbol Allegro_Viewer_Plus Allegro_design_expert
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) ^+ R+ ~( Z6 v+ l0 M1 M22:01:37 (cdslmd) Allegro_designer_suite Allegro_studio Ambit_BuildGates ; F- u2 u8 M* ?# \. q& C/ T
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2 F' t, P2 u& y22:01:37 (cdslmd) Assura_LVS Assura_MP Assura_OPC
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22:01:37 (cdslmd) Assura_RCX Assura_SI Assura_SI-TL 3 x3 ~. ?0 _% Y1 U& `2 m3 _
: A# g0 n1 m. D/ A4 D22:01:37 (cdslmd) Assura_SiMC Assura_SiVL Assura_UI
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7 u0 S6 \ W- E( n- G% z22:01:37 (cdslmd) Atmel_ATV Attsim_option_ATS Base_Digital_Body_Lib
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22:01:37 (cdslmd) Base_Verilog_Lib BoardQuest_Designer BoardQuest_Team $ f, Y- Q* ^+ j8 T2 ~& E E9 y
* p$ _' D0 i. P: u- P+ b: j$ [: L22:01:37 (cdslmd) BuildGates CELL3 CELL3_ARO - B% y% b5 S: o, u0 i- G
' J$ g0 P# F+ V1 L22:01:37 (cdslmd) CELL3_CROSSTALK CELL3_CTS CELL3_ECL
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22:01:37 (cdslmd) CELL3_OPENDEV CELL3_OPENEXE CELL3_PA : _: I3 F @ n0 `5 v) Z
u6 W0 u, ^( V, X8 S* G0 Z' b4 \22:01:37 (cdslmd) CELL3_PR CELL3_QPLACE_TIMING CELL3_SCAN
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6 F) c% G( d+ E' _ M22:01:37 (cdslmd) Capture_CIS_Studio CheckPlus Checkplus_Expert ' }9 r% Q% K( U) p5 z
( x, O8 o, d- s7 l3 A7 Z" a3 w22:01:37 (cdslmd) Cierto_HW_design_sys_2000 Cierto_SPW_CDMA_Library Cierto_SPW_GSM_VE
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22:01:37 (cdslmd) Cierto_SPW_IS136_VE Cierto_SPW_comm_lib_flt_pt Cierto_SPW_comm_library_fxp_pt
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) O) u3 g4 Q$ a) H22:01:37 (cdslmd) Cierto_SPW_link_to_Ambit_BG Cierto_SPW_link_to_NC_sim Cierto_SPW_model_manager 7 k$ |' Q* u+ @8 K4 U0 I
) ?) h( ~! P J; c% }8 G3 x22:01:37 (cdslmd) Cierto_SPW_multimedia_kit Cierto_SPW_pcscdma_VE Cierto_Wireless_LAN_Library 4 o& T# d& P2 F |, V. [& |
4 v/ V' B% j% h4 t2 n* J8 w22:01:37 (cdslmd) Cierto_signal_proc_wrksys_2000 Clock_Tree_Generation Cobra_Simulator
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22:01:37 (cdslmd) ComposerCheckPlus_AdvRules ComposerCheckPlus_Checker ComposerCheckPlus_RuleDev 2 ^% f, R/ i* p( ^! Q w; v
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22:01:37 (cdslmd) Composer_EDIF300_Connectivity Composer_EDIF300_Schematic Composer_Spectre_Sim_Solution
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22:01:37 (cdslmd) ConcICe_Option Concept-HDL ConceptHDL
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22:01:37 (cdslmd) Concept_HDL_expert Concept_HDL_rules_checker Concept_HDL_studio
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22:01:37 (cdslmd) Corners_Analysis DICRETE_LIB DISCRETE_LIB + p3 }6 Q& f" W! P/ R
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22:01:37 (cdslmd) DPbase DPbaseCell DPbaseGarray 2 I1 n' y- f j! G
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22:01:37 (cdslmd) DPcongest DPdelayCalc DPecoIpo
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2 r; Z2 d! p$ n) f% U22:01:37 (cdslmd) DPextractRC DPfasnet DPgotc ( O" u, a: B1 k1 d! O' P6 a
. j, `+ s4 B3 ^8 c22:01:37 (cdslmd) DPhyperPlaceCell DPhyperPlaceGarray DPparasitic
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22:01:37 (cdslmd) DPpearlLocked DPqplaceAB DPqplaceGA
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' [( l7 |1 g4 W1 q4 k4 h! f22:01:37 (cdslmd) DPqplaceLocked DPrcExtract DPsdfConvPR
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2 Z( ]2 ~2 e. C) d0 T22:01:37 (cdslmd) DPsynopsys DPunivInterface DPwplaceLocked
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22:01:37 (cdslmd) DRAC2CORE DRAC2DRC DRAC2LVS 1 b; f; v) q: w, N0 c% Z! M
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22:01:37 (cdslmd) DRAC3CORE DRAC3DRC DRAC3LVS + ?3 W7 ]4 |6 Y3 H0 D/ k% L* c: e3 P
2 G. J4 W) g2 A22:01:37 (cdslmd) DRACACCESS DRACDIST DRACERC # F" E" `3 `5 x& u( L/ U. ~
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22:01:37 (cdslmd) DRACLPE DRACLVS DRACPG_E 2 z, p. y0 ^" Y# _6 E1 k
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22:01:37 (cdslmd) DRACPLOT DRACPRE DRACSLAVE 0 h( k! |" u6 V
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22:01:37 (cdslmd) Datapath_Preview_Option Datapath_VHDL Datapath_Verilog y O4 j* u) H9 y
" M) S6 } z% c" i9 `22:01:37 (cdslmd) Device_Level_Placer Device_Level_Router Distributed_Dracula_Option
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22:01:37 (cdslmd) EBD_edit EBD_floorplan EBD_power , o3 t h5 S% R1 ~% f; }8 X
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5 q6 [4 R; K) ^22:01:37 (cdslmd) EMControl EMControl_Float EditBase_ALL 1 f& Z( \2 [% q" d
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22:01:37 (cdslmd) EditFST_ALL Envisia_DP_SI_design_planner Envisia_Datapath_option
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22:01:37 (cdslmd) Envisia_GE_ultra_place_route Envisia_LowPower_option Envisia_PKS 8 j& z5 V; _3 B1 I2 P, i5 f
$ _1 D2 n# A4 ~" C j22:01:37 (cdslmd) Envisia_SE_SI_place_route Envisia_SE_ultra_place_route Envisia_Utility
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$ J |7 n0 @. c0 l0 U22:01:37 (cdslmd) Envisia_synthesis_with_PKS Extended_Digital_Body_Lib Extended_Digital_Lib # u- S- l! j* H/ W7 x
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22:01:37 (cdslmd) Extended_Verilog_Lib FPGA_Flows FPGA_Tools - D- C2 M. a- ?1 b6 o
, D i# I5 d, d9 }22:01:37 (cdslmd) FUNCTION_LIB Framework GATEENSEMBLE p1 K7 ]" F) t9 m. x0 t Z: U
: G4 B/ a' e9 W" ?+ S9 L3 q' B2 v4 T22:01:37 (cdslmd) GATEENSEMBLE_ARO GATEENSEMBLE_CROSSTALK GATEENSEMBLE_CTS ! z, v0 T8 a+ q6 ^9 m; N
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22:01:37 (cdslmd) GATEENSEMBLE_CTS_LE GATEENSEMBLE_CTS_UL GATEENSEMBLE_ECL
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22:01:37 (cdslmd) GATEENSEMBLE_LOWEND GATEENSEMBLE_OPENDEV GATEENSEMBLE_OPENEXE ( a9 H7 j) u1 F, G) C8 ?
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22:01:37 (cdslmd) GATEENSEMBLE_PA GATEENSEMBLE_PR_LE GATEENSEMBLE_PR_UL
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22:01:37 (cdslmd) GATEENSEMBLE_QPLACE_TIMING GATEENSEMBLE_SCAN GATEENSEMBLE_TIMING 4 `- z: t* T8 l% I. ?
: N: R7 J6 F6 o, l' \22:01:37 (cdslmd) GATEENSEMBLE_TIMING_LE GATEENSEMBLE_TIMING_UL GATEENSEMBLE_UNLIMITED
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22:01:37 (cdslmd) GATEENSEMBLE_WIDEWIRE Gate_Ensemble_DSM HDL-DESKTOP 7 l( j0 I8 s( Q
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22:01:37 (cdslmd) HLDSbase HLDSbaseC HLDexportDPUX / _5 e% z, b7 `( P/ j# N+ f
E q! f H" S. n$ _- C. ]- v22:01:37 (cdslmd) HLDimportDPUX IDF_Bi_Directional_Interface IPlaceBase_ALL ; [; H( j" L* a9 K0 y: N
% w/ a5 e% a: z22:01:37 (cdslmd) Intrica_powerplane_builder LAS_Cell_Optimization LDPbaseCell
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22:01:37 (cdslmd) LDPbaseGarray LDPclock LDPhyperPlaceCell 4 F5 X# ]5 X% E
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22:01:37 (cdslmd) LDPhyperPlaceGarray LEAFPROG-SYS LEAPFROG-BV
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, X4 ?5 W3 A6 s22:01:37 (cdslmd) LEAPFROG-C LEAPFROG-CV LEAPFROG-SLAVE % h$ K9 w1 f9 x1 ]' O1 d# \$ C( |
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22:01:37 (cdslmd) LEAPFROG-SV LEAPFROG-SYS LEAPFROG-VC ) _, T% s# V9 S) |
7 s* W* d( T1 H# r! s# Z6 ]22:01:37 (cdslmd) LID10 LID11 LINAR_LIB
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( a. ^; u3 ^( v7 q22:01:37 (cdslmd) LINEAR-LIB LINEAR_LIB LSE 6 `/ p6 a. U& A( j
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22:01:37 (cdslmd) Layout LayoutEE LayoutEngEd
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22:01:37 (cdslmd) LayoutPlus MAG_LIB MIXAD_LIB
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( d% w( t7 s$ F* O! q22:01:37 (cdslmd) MTI_option_Attsim Model_Check_Analysis NC_VHDL_Simulator
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22:01:37 (cdslmd) NC_Verilog_Data_Prep_Compiler NC_Verilog_Simulator Nihongoconcept . m, H6 F+ P6 C8 t/ m3 ] }% a. J
6 E# V/ B2 M! K: i22:01:37 (cdslmd) OASIS_Simulation_Interface OpenModeler OpenModeler_SFI
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22:01:37 (cdslmd) OpenModeler_SWIFT OpenSim OpenWaves ) X6 [5 z; ^3 b4 I2 K. M
( a U5 |, l. Q- B22:01:37 (cdslmd) Optimizer OrCAD_Capture_CIS_option OrCAD_EE_Designer_Plus / J% s& Q8 Z5 b% ~6 ?+ y
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22:01:37 (cdslmd) OrCAD_PCB_Designer OrCAD_PCB_Designer_Basics OrCAD_PCB_Designer_PSpice
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4 W0 _- m5 I* X `7 Z22:01:37 (cdslmd) OrCAD_PCB_Editor OrCAD_PCB_Editor_Basics OrCAD_PCB_Router ( D0 t4 O1 O$ K* ~7 f/ v5 \8 B5 ]
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22:01:37 (cdslmd) OrCAD_Signal_Explorer OrCAD_Unison_EE OrCAD_Unison_PCB 0 U$ P4 U2 \, x; d2 Y
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22:01:37 (cdslmd) OrCAD_Unison_Ultra PCB_Design_studio PCB_design_expert
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22:01:37 (cdslmd) PCB_designer PCB_librarian_expert PCB_studio_variants . z# K3 r& `* k; i0 _
: [ ^5 ?% v: x1 t" y! R22:01:37 (cdslmd) PE_Librarian PICDesigner PIC_Utilities ) J7 h# y/ h! U2 R$ M. J
6 l5 s k8 y# f& d y) E% g22:01:37 (cdslmd) PLD PPR-HPPA PPRoute_ALL : b. N/ R) U( M/ K" M. m( s" k
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22:01:37 (cdslmd) PSpice PSpiceAA PSpiceAAOptimizer
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* X) q8 s1 ^3 l" g22:01:37 (cdslmd) PSpiceAAStudio PSpiceAD PSpiceBasics 9 S5 `+ W5 M6 b' b2 h
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22:01:37 (cdslmd) PSpiceOPTIOpt PSpiceOptimizer PSpicePerfOpt
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22:01:37 (cdslmd) PSpiceSLPSOpt PSpiceSmokeOpt PSpiceStudio
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22:01:37 (cdslmd) Pearl_Cell PlaceBase_ALL Placement_Based_Optimization
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22:01:37 (cdslmd) Placement_Based_Synthesis PowerIntegrity Prevail_Board_Designer
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22:01:37 (cdslmd) Prevail_Correct_By_Design Prevail_Designer Preview_Synopsys_Interface ; ~* Q3 u4 w, T- M- b: G
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22:01:37 (cdslmd) PspiceADBasics QPlace Quickturn_Model_Manager
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22:01:37 (cdslmd) RouteFST_ALL RouteHYB_ALL RouteMVIA_ALL : b& q$ ?8 P6 z3 T6 T, U* N3 Q' }
7 a: A7 e' x6 I22:01:37 (cdslmd) SDT_MODEL_MANAGER SPECCTRAQuest SPECCTRAQuest_EE
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6 C Z! v0 @; T( |6 q3 J22:01:37 (cdslmd) SPECCTRAQuest_EE_SI SPECCTRAQuest_Planner SPECCTRAQuest_SI_expert
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22:01:37 (cdslmd) SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD ' c& d3 j# q" ^* u/ g6 g. c1 x
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22:01:37 (cdslmd) SPECCTRA_DFM SPECCTRA_HP SPECCTRA_PCB * a M4 \& S" B! b
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22:01:37 (cdslmd) SPECCTRA_VT SPECCTRA_autoroute SPECCTRA_expert
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- h. X" V, r( n" N$ |22:01:37 (cdslmd) SPECCTRA_expert_system SPECCTRA_performance SPW_BDE
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22:01:37 (cdslmd) SPW_BER_Sim SPW_BVHDL_CDMA_LIB SPW_BVHDL_COMM_FXP
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22:01:37 (cdslmd) SPW_CGS_ANY SPW_CGS_C30 SPW_CGS_C40 " C9 t- _. c; s( E1 c( `5 r
8 l4 K$ D7 K1 J$ i2 i' h2 K( H22:01:37 (cdslmd) SPW_CGS_DSP32C SPW_CGS_M96002 SPW_CGS_PKB # l- L8 B! C1 x- H
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22:01:37 (cdslmd) SPW_CGS_STANDARD_C SPW_COSIM_LEAPFROG SPW_COSIM_VERILOG_XL 7 @( a3 @3 R3 d/ J8 {& @
! z- x/ D# A' Y+ j22:01:37 (cdslmd) SPW_COSIM_VSS SPW_DATA_MANAGEMENT SPW_ENV_MAT ; Q, O, t$ f P4 i3 k! W# y
+ ?. j8 C/ `. Q5 k6 d. H, h22:01:37 (cdslmd) SPW_FDS SPW_FMG SPW_FSM 6 z# _0 w. R8 Q9 w5 d, D7 {
% |& g2 @) L; X( X% {2 v6 L22:01:37 (cdslmd) SPW_HDS_VHDL_LINK SPW_HLS SPW_LIB_CDMA_LIB ) Q8 D6 u4 a# O
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. V: F3 z# q) J9 {; `* b22:01:37 (cdslmd) SPW_LIB_DSP563S SPW_LIB_DSP566S SPW_LIB_DSP568S 3 r/ u# N- F) h% j3 u* p3 @
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22:01:37 (cdslmd) SPW_LIB_DSPGROUP SPW_LIB_GSM_LIB SPW_LIB_HDS_ARC
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5 |% j. M7 x) T" Q3 j" _# t; k22:01:37 (cdslmd) SPW_LIB_HDS_ISL SPW_LIB_HDS_LIB SPW_LIB_HDS_MAIN ( W8 C1 D3 j2 \
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22:01:37 (cdslmd) SPW_LIB_HDS_MICRO SPW_LIB_IS136LIB SPW_LIB_IS95LIB
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22:01:37 (cdslmd) SPW_LIB_MDK SPW_LIB_RADAR SPW_LIB_RF_LIB 0 E6 n0 n9 Z* ?+ s- T) a
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22:01:37 (cdslmd) SPW_LIB_VFL SPW_LINK_VERILOG SPW_LINK_VHDL
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7 z5 b6 g2 [+ N2 ^$ G4 e/ R22:01:37 (cdslmd) SPW_LINK_VHDL_BEH SPW_LSF_Link SPW_MODEL_MANAGER
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7 e$ \# X3 w& l% U22:01:37 (cdslmd) SPW_MPX SPW_SIGCALC SPW_SIM
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+ c8 g' i% l$ r: ^6 v( F22:01:37 (cdslmd) SPW_SIM_UI SPW_Smart_Antenna_Library SQ_Digital_Logic_SI_Lib
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22:01:37 (cdslmd) SQ_FPGA_SI_Lib SQ_Memory_SI_Lib SQ_Microprocessor_SI_Lib ' M: z& v m f u3 F9 g
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22:01:37 (cdslmd) SQ_ModelIntegrity SWIFT Schematic_Generator
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22:01:37 (cdslmd) SiP_Digital_Architect_GXL SiP_Digital_Architect_GXL_II SiP_Digital_Architect_XL
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7 h: z' \1 s1 ?3 e22:01:37 (cdslmd) SiP_Digital_Layout_GXL SiP_Digital_SI_XL SiP_Digital_SI_XL_II ' T. w- ]2 T4 q" X' P
- o5 ]3 _! ?7 S& n+ F# y22:01:37 (cdslmd) SiP_RF_Architect SiP_RF_Architect_XL SiP_RF_Layout_GXL
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22:01:37 (cdslmd) SiP_RF_Layout_GXL_II SigNoise SigNoiseCS
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22:01:37 (cdslmd) SigNoiseEngineer SigNoiseExpert SigNoiseStdDigLib ' n# b/ n* c$ C/ d- ^. u" y; g
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22:01:37 (cdslmd) SigNoise_Float SiliconQuest Silicon_Ensemble
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22:01:37 (cdslmd) Silicon_Ensemble_CTS Silicon_Ensemble_DSM Silicon_Ensemble_DSM_Crosstalk 5 p3 i8 ]& O: q
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) X5 ]/ ~& s3 z* J22:01:37 (cdslmd) SimVision SpectreBasic SpectreRF
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6 L# B8 F: r& e0 z22:01:37 (cdslmd) Spectre_BTAHVMOS_Models Spectre_BTASOI_Models Spectre_NorTel_Models & b& u( b: \: K4 g0 S, a" t
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22:01:37 (cdslmd) Spectre_ST_Models Substrate_Coupling_Analysis Synlink_Interface
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: C, e4 O, O- \) P22:01:37 (cdslmd) TOPOLOGY_EDITOR Trans_level_option_Attsim UET & X; m2 m& O2 K( r
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22:01:37 (cdslmd) UNISON_SPECCTRA_6U Unison_SPECCTRA_4U Universal_Smartpath
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. Z# d" n5 \/ ~5 h% H3 `) H+ l22:01:37 (cdslmd) VB_6SUPUC_ALL VCC_Editors VCC_SW_Estimator ; K+ W* `7 k3 h4 S
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& p9 f8 v) j/ s+ U22:01:37 (cdslmd) VERILOG-XL VERITIME VERLOG-SLAVE ( R A. y& ?: z4 M4 a
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22:01:37 (cdslmd) VHDLLink VITAL-XL VXL-ALPHA
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h; S$ }1 ]- @5 U22:01:37 (cdslmd) VXL-VRA Vampire_HDRC Vampire_HLVS % U% \$ d: [: e# y7 g
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22:01:37 (cdslmd) Verif_Ckpit_Analysis_Env Verif_Ckpit_Runtime_Env ViewBase
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22:01:37 (cdslmd) ViewBase_ALL Virtuoso_Core_Characterizer Virtuoso_Core_Optimizer
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22:01:37 (cdslmd) Virtuoso_Schem_Option Virtuoso_SiI Virtuoso_Turbo * W# p7 W+ B% C
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22:01:37 (cdslmd) Virtuoso_XL Virtuoso_custom_placer Virtuoso_custom_router
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22:01:37 (cdslmd) XBLOX-HPPA XDE-HPPA _21900 ; |! B( o6 Y/ [
- Z% {8 Z' u2 }* D: U22:01:37 (cdslmd) a2dxf actomd adv_package_designer
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22:01:37 (cdslmd) adv_package_designer_expert adv_package_engineer_expert allegro_dfa
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' L/ T5 z" X1 u, n+ a# h22:01:37 (cdslmd) allegro_dfa_att allegro_non_partner allegroprance 6 k1 c! y( c$ }7 S
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22:01:37 (cdslmd) caeviews cals_out cbds_in
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22:01:37 (cdslmd) cdxe_in comp concept , g8 N, S% J7 `/ h: Z8 q. O
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22:01:37 (cdslmd) cpe cpte crefer 6 G$ _( y7 u8 k
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22:01:37 (cdslmd) cvtomd debug dfsverifault ( Q$ e! A: \% X% u8 v' R
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( W2 d3 n5 V; r22:01:37 (cdslmd) eCapture edif-HPPA edif2ged
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22:01:37 (cdslmd) expgen fcengine fcheck 0 M1 W) |/ L, ^
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22:01:37 (cdslmd) fethman fetsetup gbom . w$ U9 {, U/ s0 [# @( I
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22:01:37 (cdslmd) ged2edif gilbert glib
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1 N% \4 c# G( ~& }$ o& H22:01:37 (cdslmd) gloss gphysdly gscald 7 G B, y: [. ]
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22:01:37 (cdslmd) gspares hp3070 hyperExtract 2 Y0 F2 v4 D: c- u- l$ R
0 b: r! \# m( m* T6 h! B! g% p! E22:01:37 (cdslmd) hyperRules iges_electrical intrgloss
1 _( ?- ~8 [0 A& P% I
' {$ a& t9 y* ~6 z; X1 a22:01:37 (cdslmd) intrroute intrsignoise ipc_in 0 c2 I- G2 [, t+ `2 K, ]6 G5 _
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22:01:37 (cdslmd) ipc_out libcompile lwb ; N6 a' X7 N( t2 |9 R1 J
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22:01:37 (cdslmd) mdin mdout mdtoac
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9 M5 |$ N b9 f' O6 u9 N22:01:37 (cdslmd) mdtocv multiwire odan T( H8 j- M2 R) A3 R' L
, n( }7 F: ~9 y7 M22:01:37 (cdslmd) packager partner pcb_cursor 2 w3 _/ s8 Q$ g+ f* H
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22:01:37 (cdslmd) pcb_editor pcb_engineer pcb_interactive 4 b, b% g& `: L" a
% [8 B I9 }( z+ i* f3 I22:01:37 (cdslmd) pcb_prep pcb_review pcomp + m: V! e% k4 d+ S: P; {3 d
, {( e/ O) ], T; r+ _ ]' G22:01:37 (cdslmd) pillar.abstract pillar.areaPdp pillar.areaPlanner
1 L7 S; F( h; I9 b- b( Y& U8 U/ i. j- I" |) T6 A/ G
22:01:37 (cdslmd) pillar.cdsIn pillar.cdsOut pillar.cellPdp
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22:01:37 (cdslmd) pillar.cellPlanner pillar.db pillar.dbdev
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22:01:37 (cdslmd) pillar.dbperl pillar.defIn pillar.defOut
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& w% z( u8 U! X5 @6 t2 y% r. f22:01:37 (cdslmd) pillar.edifIn pillar.edifOut pillar.gatePdp
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0 U% d2 j/ L( S' n+ g22:01:37 (cdslmd) pillar.gatePlanner pillar.gdsIn pillar.gdsOut % |- |# Q: j( N: G1 V
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22:01:37 (cdslmd) pillar.ge pillar.gui pillar.ldexpand
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5 D. E/ W: i s8 e" i22:01:37 (cdslmd) pillar.lefIn pillar.lefOut pillar.pdp
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22:01:37 (cdslmd) pillar.verIn pillar.verOut pillar.vhdlIn
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/ L$ [ B/ T4 Y/ g+ \/ p/ F" r22:01:37 (cdslmd) pillar.vhdlOut pillar.vre pillar.xl " p, Y( U9 x& }
- O+ Z3 Y; z( n/ u22:01:37 (cdslmd) pillar.xlcm pillar.xldev placement 0 M9 X7 J0 I) i
0 k4 @8 ` N( R, b+ a22:01:37 (cdslmd) plotVersa ptc_in ptc_out
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& B1 ~: x! Z$ ?9 y w22:01:37 (cdslmd) quanticout rapidsim realchiplm 3 g I; ~2 `( G4 Y% h
2 b; w6 M8 ^# }# o22:01:37 (cdslmd) redifnet rt sdrc_in
5 `' h9 _6 x+ x4 s L/ o7 {
4 Y; r( O/ Y7 d2 r22:01:37 (cdslmd) sdrc_out shapefill sigxp * _& o {8 Y, M- w3 {
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22:01:37 (cdslmd) skillDev sqpkg stream_in
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' n* i/ o- O+ p2 r2 o4 }4 o9 F/ P22:01:37 (cdslmd) synSmartIF synSmartLib synTiOpt 1 y1 O) Q7 d9 t
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22:01:37 (cdslmd) tsTSynVHDL tsTSynVLOG tsTestGen - b9 Z' Y9 |9 b) H r# i
+ u7 G6 f( z( t& Z6 D, {22:01:37 (cdslmd) tsTestIntf tscr.ex tune ! H( k4 v3 t: k7 `; k
7 h3 i5 s$ S1 l3 G: _- T22:01:37 (cdslmd) tw01 tw02 v2e 0 _6 g; g7 N4 X9 p$ H
+ X& a2 c3 a, x3 O: z- {' z22:01:37 (cdslmd) verfault verifault vgen ; i, |/ Q7 W5 C) [4 R/ y W
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22:01:37 (cdslmd) viable visula_in vloglink $ b/ z0 C) u3 e) n7 U+ _2 L3 ?/ o+ _
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22:01:37 (cdslmd) wedifsch xilCds xilComposerFE
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22:01:37 (cdslmd) xilConceptFE xilEdif OrCAD_FPGA_System_Planner
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- {4 E5 _% h; M* o/ y22:01:37 (cdslmd) Allegro_FPGA_System_Planner_L Allegro_FPGA_System_Planner_XL Allegro_FPGA_System_Plan_GXL
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22:01:37 (cdslmd) Allegro_FPGA_System_2FPGA Allegro_Design_Publisher
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22:01:37 (cdslmd) 8 |) e4 P8 b# }! L9 y, h
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22:01:37 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines/ |2 _+ ]) b. w1 ]2 Y9 v
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22:01:37 (cdslmd)
1 [9 F) {7 X. P2 p/ @6 z+ q+ [, n5 i- q' E5 t3 x! c# J
22:01:37 (cdslmd) EXTERNAL FILTERS are OFF
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, l7 _- x) P; w$ Q7 @22:01:37 (cdslmd) CANNOT OPEN options file ".exe"+ y3 C/ f# u$ f$ z7 s
( L9 I: m8 a: j% r' F22:01:37 (lmgrd) cdslmd using TCP-port 1228
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# u1 ?9 G# ]5 e& n% d) Y22:01:42 (cdslmd) TCP_NODELAY NOT enabled0 |+ T+ S& Q9 R3 r& }
: o& J5 q% g. c22:01:43 (cdslmd) OUT: "100" Administrator@3C68B4367E914FC 9 R R2 c7 p+ j6 U$ O: B* [
2 ?. {+ Y" O( W0 [
22:01:43 (cdslmd) IN: "100" Administrator@3C68B4367E914FC |
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