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换了nandflash后和加焊DDR后有两种状态，但是板子都没有启动成功，串口有打印。
8 A+ n7 _6 h; R, d以下是状态1的log:6 x4 H* n0 |3 ^6 Q
SoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)
: L# l/ ~) ?& i" r1 mII: Stack @ 0x9fc1fd18 (parameter 736B)
4 e/ `' ~# J- y0 _II: Console... OK
t4 M4 X+ s# U! |+ @Setting DTR. z: M( y+ W" J. E0 f
II: DRAM is set by software calibration... PASSED$ Y. v$ k. O; T
% y( U2 J- x# a& A9 f
DDRKODL(0xb800021c):0x00000410; [/ P# ~# f! ]$ J
MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f% I s7 t* P" w; O- |* e
DTR2(0xb8001010):0x0630d000
0 c- N4 S; ~/ K* j$ o7 Y" QPHY Registers(0xb8001500):
& ?5 E# ], E; i _9 j* X0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xfdffffff
% Z7 B/ z. M+ ?, ]0xb8001510:0x00140a00, 0x00180c00, 0x00140a00, 0x00180c00
& E" ^3 f7 H. }0xb8001520:0x001a0d00, 0x00140a00, 0x00160b00, 0x00120900
, i& b, A+ M- V4 E, z1 M0xb8001530:0x001c0e00, 0x001e0f00, 0x001c0e00, 0x001e0f00. H1 }- f$ Q8 u. o, [9 _# X
0xb8001540:0x001e0f00, 0x001a0d00, 0x001c0e00, 0x001a0d004 R* n+ Z5 a3 M' y' A! N
0xb8001550:0x00100800, 0x00140a00, 0x00100800, 0x00140a00, w" m, V4 H$ ]1 O u! Q- T) Y
0xb8001560:0x00160b00, 0x00120900, 0x00140a00, 0x00100800
! p8 I1 a6 A+ N+ J3 b0 m' Z, e* w" X0xb8001570:0x001a0d00, 0x001a0d00, 0x00180c00, 0x001c0e00
# j0 q1 B( _7 ~6 P0xb8001580:0x001c0e00, 0x00180c00, 0x001a0d00, 0x00180c006 f; g- L6 H, l# O9 y$ N
0xb8001590:0x00000000, 0x5110dbd9, 0xa9a95656, 0x5352b5b5
, j* M8 B, m8 |( ~3 d0xb80015a0:0x4145dcdc, 0x00000000, 0x00000000, 0x000000003 z* B8 Y( l/ O, c
II: PLL is set by SW... OK' A3 c# `' t1 i, B
II: Flash... OK
5 h, k4 i7 f' K6 a' i" rII: Stack @ 0x801ffff8
. r3 M% N1 y: X. Y0 DII: Starting U-Boot...
; P! v, g+ c3 n, r* v7 ?5 D, [# ?- TII: Inflating U-Boot (0x80000040 -> 0x87c00000)... ! U- U* R3 Y5 j- O$ c' O
EE: decompress failed: 1
$ \8 A; m8 Q2 @6 L以下是状态2板了log:
h! d C/ O5 {* K3 BSoC preloader 1.0.0.r1422.lzma (Wed Nov 13 14:32:57 CST 2013)
' w) u5 e/ L# _0 d$ e% SII: Stack @ 0x9fc1fd18 (parameter 736B)
% j4 X/ C3 d# F8 qII: Console... OK
/ Q7 Z9 P2 R0 p( A. MSetting DTR( N( |4 `; o _/ G1 j2 f3 Q- M
II: DRAM is set by software calibration... PASSED
F3 O* y1 q6 l! G9 l& w! r; }( K! @) f0 `( N5 p
DDRKODL(0xb800021c):0x00000410. O5 S" ^/ U0 @7 D# T; g/ w
MCR (0xb8001000):0x22041de0, 0x21220000, 0x54433830, 0x0404030f
4 j* E; k6 f3 _; FDTR2(0xb8001010):0x0630d000/ x0 B' }( y/ E) p8 I+ m1 T5 M
PHY Registers(0xb8001500):; t% i8 ~8 b( ^8 U) d" Y% a+ O
0xb8001500:0x80000010, 0x0000007f, 0xa1a00000, 0xffffffff7 O! ]! S* |5 T
0xb8001510:0x00120900, 0x00140a00, 0x00120900, 0x00160b00
$ M) y( u+ O" e0 P6 G0xb8001520:0x00140a00, 0x00120900, 0x00140a00, 0x00100800
& g) r: B8 l, G2 Z) i4 X0xb8001530:0x00180c00, 0x001a0d00, 0x00180c00, 0x001a0d00
. g: O% K) w7 N6 D3 x! ` q0xb8001540:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c00
( _- Q2 B8 x4 d0xb8001550:0x00120900, 0x00160b00, 0x00120900, 0x00140a00* K0 L1 W2 T1 S, J3 G- b, M
0xb8001560:0x00140a00, 0x00140a00, 0x00120900, 0x00100800
1 x8 o) \: @- V$ p# A0xb8001570:0x001c0e00, 0x001c0e00, 0x00180c00, 0x001c0e00
1 C0 N- o h' \1 [0xb8001580:0x001a0d00, 0x00180c00, 0x001a0d00, 0x00180c000 t' s- ^6 o, S2 w1 o7 }1 ]0 k( b
0xb8001590:0x00000000, 0x5adad2d2, 0x24207574, 0x5a5adada, R S; P" l4 M! ~3 e, \ }2 S
0xb80015a0:0x8d0da7a5, 0x00000000, 0x00000000, 0x00000000+ u/ X2 q0 P5 C( I; ?
II: PLL is set by SW... OK6 b. |6 L. W" v: u' w, _
II: Flash... OK
% n0 h+ o- f/ f# c6 }II: Stack @ 0x801ffff8
* P2 e4 ^& @* M- q5 E! p6 s) ^II: Starting U-Boot...
8 l+ L8 H1 f8 U: ^1 [II: Inflating U-Boot (0x80000040 -> 0x87c00000)... OK1 W/ r2 P4 F1 G e
II: Starting U-Boot... ! {! g6 B. \* {# b: t
M9 i1 S) P; P! I" e( \% \
+ m& O3 P; E& A& w/ \U-Boot 2011.12.NA (Nov 13 2013 - 14:33:03)7 {! i4 {9 U: n
; |7 o- Z# O: @3 S' |1 r, p0 u# ~
Board: LUNA
) d& H) c3 L( |- G) m) J" eCPU: RLX5281 600.00 MHz, DSP: RLX5181 500.00 MHz, , DDR3 300MHz, LX:200.00 MHz ) {) w# N- E7 D! X8 m: c$ A
DRAM: 128 MB. _# I: x+ e9 }: z5 l
enter nand_init* v1 [6 K6 O A1 E+ x
board_nand_init()
1 o( c6 p' F, k3 N" `6 s0 Lparameters at 0x00001212
7 q2 s% c% M! @; z+ Vparameters.read at 0x9fc00550+ @5 [% M; W T: }$ l
parameters.write at 0x9fc03308
, p+ I/ T6 P7 X, pparameters.bbt at 0x9fc1feac% f/ I: s5 l4 @0 z% O4 s8 ]2 J: W$ q
uboot- read nand flash info from SRAM2 m, k* M5 X4 o$ V9 y* Y9 {% D4 H( l
flash_info list0 l/ j: b7 \, X2 L l' `) c: |
flash_info.num_block : 1024
1 ]' O4 d8 t! h6 ?+ Oflash_info.num_page_per_block : 64' B) P* n; L0 _( E- y, M: p
flash_info.page_per_chunk : 1
" g( Y y6 A4 t: }flash_info.bbi_dma_offset : 2000
; J/ ~, _1 _. N6 qflash_info.bbi_raw_offset : 2048% c7 a3 U1 m0 H" y
flash_info.bbi_swap_offset : 235 H+ b0 A1 p4 R6 ?) d4 \
flash_info.page_size : 20484 I- R: \) C" R9 z9 X% f: z
chunk size : 20485 C* \3 X( P+ g$ n
flash_info.addr_cycles : 4; q! g9 K' ]2 F. a7 _) b- Q+ K
pblr_start_block : 1$ N5 G% g* ~) R
num_pblr_block : 3: V8 h9 L _0 Z& ~' S9 ?) Q- v
parameters.curr_ver is a& c/ O" Q. D" n/ R7 T0 R
parameters.plr_num_chunk is 299 d5 n# R V( g
parameters.blr_num_chunk is 45
. z4 Y2 s9 {+ ~9 g2 [parameters.end_pblr_block is 42 W3 l; V) c- U- [# M3 G3 ]
rtk_nand_read_id id_chain is 9580f1928 w3 @, D9 w! L1 X8 s( T: Q
nand: Manufacture ID=0x92, Chip ID=0xf1, 3thID=0x80, 4thID=0x95, 5thID=0x40, 6thID=0xc0& V; Q2 `, o. `3 e- F- Z
this->pagemask is 65535
( p9 H5 O" L! B2 ~( P) }this->chip_shift is 27' K4 }1 S, k& F/ Q9 q& y1 N. l# C
parameters.bbt_valid is 1+ X% t7 g3 j& x7 V5 e7 e
create_logical_skip_bbt! F9 ^6 g; Y |4 ] }1 J
last skip_block 1024
7 \- \5 n) d5 ^) Qnand.c nand_init_chip mtd size is 877bfeac7 }- [3 X# W6 m9 n; h
128 MiB
* ]9 O( _3 T+ v: R2 B [; I, dLoading 131072B env. variables from offset 0xc0000
0 S' ?( ^' ^# U$ T5 W, t6 Y4 lUnknown command 'sf' - try 'help'5 d3 A4 S0 h! A$ h" W5 z5 q0 J
Net: LUNA GMAC
9 M$ r/ x' A7 q' b/ N G2 d( RWarning: eth device name has a space!
. p5 ]# G3 [% e% x7 x1 F1 B8 I) S3 q) u! K4 w4 m; j/ _
Hit space key to stop autoboot: 0 C, R j& ]* ~9 Z5 p
" t9 i; w: l8 @6 T4 x
8 y# W0 H, }2 fACTIVE IMAGE 0 (tryactive=2 sw_commit=0)
7 i. I( I, G# E9 A5 P7 e: u
% y5 P7 |7 Z- q! L1 greset pcie05 \7 Y9 O9 L. F# \! Q- x
reset pcie1 V+ N6 d; X% X% C, R' c
9 t3 G* A1 d" r1 C
NAND read: device 0 offset 0x100000, size 0x3800008 X$ T& l! Y# K8 W
3670016 bytes read: OK4 f! L5 p! |3 l! E
## Booting kernel from Legacy Image at 82000000 ...7 M3 Z7 G# I3 t! {5 y# J$ x
Image Name: Linux-2.6.302 I# S3 F( [1 J( c; y; M" |
Created: 2013-11-14 2:56:37 UTC' d4 I( \1 b9 _4 F* V
Image Type: MIPS Linux Kernel Image (lzma compressed)
1 r2 g: S/ p; ^) H1 s/ _ Data Size: 1791872 Bytes = 1.7 MB8 A# Y; h$ G5 i) m& i
Load Address: 80000000( P/ s6 a7 H; l' d0 @2 y" D6 T; x* q3 p
Entry Point: 80000000
! c$ F: F: K0 R. I& w' h Verifying Checksum ... Bad Data CRC" D8 e. k! C! H7 K
ERROR: can't get kernel image!
" Z) w1 [6 g" t3 V+ r5VT-2510# . Q" M" ]$ D: Y( ?7 R& X& L& q
请问大家这是什么问题呢？ |
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/1 
发表于 2013-11-28 17:40
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