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本帖最后由 pzt648485640 于 2013-11-19 08:22 编辑 ) ~! E# {% u) H! u; d$ A
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http://pan.baidu.com/share/link? ... 9&uk=2033524562" f5 I- w) X; }2 p2 |+ T7 U, L
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DATE: 11-15-2013 HOTFIX VERSION: 019& {8 C0 d- [8 ]1 R& i, z; J
& B, \* ~7 K) \* n6 W) J=================================================================================================================================== `# ~: d4 S- R" y& m" N/ [
3 S0 Q- y$ }! J# ?6 pCCRID PRODUCT PRODUCTLEVEL2 TITLE
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9 ^! h7 |! O q6 p1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3
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1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly2 b. ]2 \' ]. n9 e3 Z9 w$ J
9 }& f) _- _3 A1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.5 N# j: a) ~3 @( H6 x; p% s
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1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings
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9 s! M9 f# y* \1 V( y9 T! \% N1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.
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1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to ¿Miscellaneous Image Layers¿ should automatically get selected6 v0 r) _' H2 n l/ J3 I
1 f6 u) q& Z* ?. F* ?6 v4 ?6 G1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product, A" \. u# l ~+ f
7 f! x! Y, F, A) S. ]1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.
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8 H% ^, m$ C3 ~9 v8 ]( ]1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path
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1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.
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1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping. c5 X/ k0 c9 w1 K) o
" c+ g- }9 P5 \7 i' R' C+ B- n& g1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.
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9 c7 l, q/ e2 z% ]6 t% o6 z1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro
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1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode/ e. ^/ j8 g" D3 c2 c8 e
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1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing., f; s1 e' g8 A" K! H
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1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.
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% U% h. j& T+ W/ P1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs% F$ q) R. K6 W" k+ G G
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1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017$ e6 S8 E" [" C
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1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor
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7 y3 n5 S- j# h& ^1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout Z$ d7 P9 R% N. F# K
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1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
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% i0 V! O0 T& g' Y1 V2 z- M- B) _1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct2 w( G \& n$ K6 v5 x Y' m" Y, ~
) F# d5 ?: Q& v! G) m* V" ~6 t1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure., Q; ~. c& l2 o
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1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error
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* S- E: H& \8 ?1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails
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1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga7 `! x+ l* ]6 o1 @
X$ X& I7 e5 T; S3 T1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.
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1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.
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1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor$ d& @$ o! c: p
0 W" r/ w/ N1 q$ M$ \: W! R0 }1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.2 Y0 P$ d$ u! k1 I
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1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro
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发表于 2013-11-18 09:19
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