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Cadence SPB OrCAD 16 最新的升级补丁，版本号16.50.46，修正内容如下：
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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5 e$ O+ `* q+ R( m5 i! j1079538 F2B PACKAGERXL Ability to block all їsingle noded netsї to the board while packaging.
" S f y6 v8 l* Q1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.; ~2 U% v: b$ U+ t& m/ h
1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
- O s' L/ ^; M* b4 o i3 \1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value
1 I) O3 J( q, |! n1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore z2 [' |$ Q1 {5 x
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.
! Z1 h. B6 i3 k$ M1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
6 v* k. z9 N6 J) g0 G* I* H1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory
/ {9 B& v1 ]& F; C1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
0 W, f# _5 o" D# P/ o3 O, a1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.- h0 d5 e+ ~3 `% Z% s: {0 N6 |
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted8 R0 c3 p: A. a& p2 y
1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.
% n p2 p3 t6 t) ]; p1 _1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.: p: L/ b# L8 Z8 G/ t* v4 I% w# J
1160004 SCM UI The RMB->Paste does not insert signal names.
+ R3 r4 P& L" s" V& g1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
+ M7 J- _2 \4 D0 {: t! A/ \1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.& ^6 ~& v8 d( b( J
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE; Q* G: F7 V. P6 [! L$ G6 E
1165469 CONCEPT_HDL CORE Import Design loses design library name; g6 r6 E- `; v3 p, t
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.0 Q0 F' c) o) a+ c
1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
4 v8 o% U: C9 J: [1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue- n' e7 ?; a9 [+ h4 }2 E' {2 e. k" x
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.% w$ J1 ]( P3 u# Q
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0 H7 s% U6 L5 ?& oCadence SPB OrCAD 16.50.46 Hotfix% {/ U ?* G, ?0 z9 S$ }, K% G& g
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Download uploaded0 z. W: K! A8 m) `# O8 k# p
http://uploaded.net/file/9yjz448a/cpborc165046ho.rar# k0 D; N/ R) O& r; X) P$ \9 F
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Download 城通网盘
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发表于 2013-8-28 21:42
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