菜鸟求组:仿真multi-threshold cmos,实现NAND gate

ak11112222ak

source 总是出现以下问题，描述的时候已经说了是接地的了啊，为什么还是会当作断开的呢？
! E' h! \+ I- C5 sCircuit: *Main mtcoms file
/ _$ N% x1 U6 k' n# t$ w
Warning: There are nodes with less than 2 connections.
3 J! n4 J2 l) O5 U. NThe table of nodes with less than 2 connections is generated after sourcing...
5 _( G. {7 c) f) s


***warning***: the following singular supplies were terminated to 1 meg resistor

supply       node1            node2
vdd           vdd                  0
v1           a                  0
6 R* q3 m& y- u& E9 O) y* K9 a4 e% Bv2           b                  0
$ t$ r6 Q9 d7 d* G: E# a3 Sv3           sl                  0


The following nodes have less than 2 connections:
-------------------------------------------------------------------------------------
$ `3 v7 }: e) r| sl                 | b                  | a                  | vdd                |
-------------------------------------------------------------------------------------
* Y% l) X3 I7 l4 F; [* d一个描述netlist的文件：
8 A5 d2 W7 H% ]) m: t6 |% h

* SPICE export by:  S-Edit 15.13
! c* Z. _/ g3 a* ?, b0 j0 M  I& s* Export time:      Tue Jun 12 11:15:52 2012
7 z6 {$ ?" i( u5 \, l$ z& J2 q* Design:           mtcoms
* Cell:             Cell0
* Interface:        VResistor
* View:             VResistor
* View type:        connectivity
* W1 n; |4 T; Z% F6 ^* Export as:        top-level cell
- m8 e- G+ z6 G. N* Export mode:      hierarchical
& [0 u4 F9 _( O1 U7 s- M* Exclude empty cells: no
* Exclude .model:   yes
* Exclude .end:     no
* Exclude simulator commands:     no
5 N: K7 ]6 U6 U/ s1 d& O" S+ H* Expand paths:     yes
* Wrap lines:       80 characters
, v+ k. F5 d: L' B7 {8 {0 R. b% [* Root path:        \\en-file\users\houx\Profile\Desktop\ankun_dong hw2\mtcoms
* Exclude global pins:   no
0 t5 }7 m# C" V/ R6 c# S  A* Exclude instance locations: no
# m, i/ n, \$ O8 D9 D0 h* Control property name: SPICE

- l  Q2 g8 Y, A# g; L. V8 t, z' k+ B( _( S********* Simulation Settings - General Section *********

" a0 d) m  ^) H9 T*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd  
" w! J* }6 y1 o  i6 D
*-------- Devices With SPICE.ORDER < 0.0  --------
* U* D. x' l3 u+ T# T* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
/ G8 d% }$ X/ z0 K' O* Info: Inverter
- e) Z7 c! L3 e) d& R: n* Date: 06/13/07 16:17:11
+ n% z1 U6 E7 ]4 C* g$ r/ e* Revision: 3 $ $x=7600 $y=600 $w=3600 $h=1200

4 l" H8 {* X* b4 P( ?; M; e*-------- Devices With SPICE.ORDER > 0.0  --------
) {$ |3 ]5 x5 v8 PMN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=4600 $y=2600
" ?# E9 i) C; E" F5 }+$w=400 $h=600
; R  V+ v$ @5 b: J* ~$ DMP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u $
+$x=4600 $y=3600 $w=400 $h=600
1 a3 ]1 E2 X' ]/ c* \0 B.ends

. F  }6 H! J4 M3 R
/ B4 K8 k  h& g: c- x5 H
/ G+ s/ k4 a. V3 ?7 Z*-------- Devices With SPICE.ORDER == 0.0  --------
( F. O( w9 F) W" v, o***** Top Level *****
XINV_1 SL N_2 Gnd Vdd INV $ $x=350 $y=-2300 $w=900 $h=600

*-------- Devices With SPICE.ORDER > 0.0  --------
CCapacitor_1 VDDV Gnd  1p $ $x=3100 $y=-400 $w=400 $h=600
CCapacitor_2 GNDV Gnd  1p $ $x=3100 $y=-2500 $w=400 $h=600
MNMOS_1 Out A N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
# P& a: }% F- F; n' Q+$y=-800 $w=400 $h=600
5 n; |' _# Q/ fMNMOS_2 N_1 B GNDV GNDV NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
, J9 Q  `+ e8 r8 K/ {1 w+$y=-1500 $w=400 $h=600
MNMOS_3 GNDV N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
* ?2 o& }* V9 k+$x=1100 $y=-2300 $w=400 $h=600
MPMOS_1 Out A VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=300
& q! }7 n0 w) Q) t  p! V  U( I+$y=-200 $w=400 $h=600
MPMOS_2 Out B VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1900
) D7 @  [: o7 ]5 c3 V# [$ K+$y=-200 $w=400 $h=600
MPMOS_3 VDDV SL Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
" {8 D  V: j$ _( h# Z/ V+$y=700 $w=400 $h=600

********* Simulation Settings - Analysis Section *********
.op

********* Simulation Settings - Additional SPICE Commands *********
4 e# |! ^2 j8 E# _- c
0 K- i' p; n5 R$ E.end

2 M  J' S# n/ n  J: ~

icy88

source接地的描述应该是 vdd vdd 0 0,你后面少个电压的值