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Translating E:\WORK\TEST\1.asc.
$ V) }$ N" [' j% wReading PADS ASCII file header.0 u& K9 H1 i% ^0 K
Version = PowerPCB5.08 } l, d7 y z$ q* ]+ u2 H. X
Route Layers = 47 h9 Y, @; B5 g/ D/ t* ~7 y4 {
Units = METRIC1 y @0 p) X" S# h+ T
Hatch mode = Vertical / Horizontal
6 j& j/ x. n8 |6 V; ` Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.000315: r; ~4 ^" T* H& U
Initializing new database.
0 C4 ~% u5 X# h+ O2 J7 C/ g Creating layers.
. v; [1 ?. d, yReading PADS ASCII file body.: o C2 g7 {/ T5 z" c% ~; e
*PARTTYPE*
; l9 O& j* n& L *MISC*
+ Z. z1 v5 F! l/ Y7 f( h1 C- p* c3 q *MISC*
0 ^4 z% f. I/ @5 F+ B *MISC*% }7 Y, l/ Z3 c
*MISC*
7 q9 L% I& @9 q2 I1 o *MISC*
. q4 }' m& }4 r- R$ M/ h) G *REUSE*% j* m0 c6 s4 z* F5 l
*TEXT*
* {4 ?5 C% c/ ` a; _2 t# _ *LINES*% \% q. _% F( c! _: g6 X# m& ~- m
*VIA*
) ^ P' F8 b* Y) |/ U a7 s, U *PARTDECAL*
) C. x) }" j$ V) d5 G *PARTTYPE*0 d* A1 p W' S/ x' v
*PART*
% H A: ~; ^8 ?+ _ *ROUTE*0 w" s q% J* z5 P4 M5 Q9 ~
Writing routes.3 d2 c. Q7 r# T, q1 i
*END*
8 t% F9 W+ P$ b( q5 A/ H1 g
; z0 w/ d* b% f! L' T===============================================================================) {4 N+ }5 m: b- B" G& z7 W; ?
PADS layer usage summary:- }" y5 j. l$ s) x8 E8 n
Layers 1 to 4 are route layers.3 Z6 y! O" E: N, X: X; {6 x
LINES:. n2 }7 ` z/ h) u1 A4 ^) Y9 W
0 BOARD GEOMETRY - ALL
1 H9 [4 ?7 q9 g1 b 1 ETCH - TOP) l8 g n8 u& R# n
3 ETCH - INTERNAL2
; `' ?0 H9 c o! k) P: E 4 ETCH - BOTTOM! P1 P. G& }; Y2 h/ z8 ?
9 * Not mapped!
' O; u1 m7 W2 q4 A7 | 10 * Not mapped!
- Y8 ?9 j) F; |% Z p! S9 _3 _ COPPER:
2 K" s1 U5 h" {- ]" X TEXT:1 g0 y n; \/ s$ ]) Q
1 ETCH - TOP
5 B( }2 e- ~3 M4 d 26 * Not mapped!# N V7 I" k- C; ^! k: B
DECALS:
# w9 b* J3 |$ ~- |( e 0 PACKAGE GEOMETRY - SILKSCREEN_TOP
; q" o- m) \2 r: M" x6 f( K! F 1 PACKAGE GEOMETRY - SILKSCREEN_TOP- W0 }$ i4 p, J
12 * Not mapped!- `7 ?4 C" r4 V6 s$ [
19 * Not mapped!
8 I( @( e1 d h 26 * Not mapped!/ l |' Y; F2 S
PADS:
7 ?( U' y, ?: o$ e% z" S 0 ETCH - internal_pad_def0 s+ y: i7 C" P. {
1 ETCH - TOP2 Q' M! V( I# ^6 N' R$ S7 k
2 ETCH - INTERNAL1
: q4 _6 x4 n: F% A2 R 3 ETCH - INTERNAL2, P5 G& x6 d" z1 G& q$ }! W
4 ETCH - BOTTOM4 d; Y* i Y( W6 K- _0 b r
6 * Not mapped!
p2 M# m5 \* y' Z+ m 15 * Not mapped!
# w) r) `7 U, s) I( \ 16 * Not mapped!0 s& u2 Y0 V \; t, @
23 * Not mapped! G2 ^" i- u4 k& y% y: d! m
VIAS:5 o& ~- Z$ [. Y/ P1 ] o: v
0 VIA CLASS - internal_pad_def" s# w+ Z7 T& t% Q' l6 e$ n
1 VIA CLASS - TOP
@( u& B9 s0 ~ i 2 VIA CLASS - INTERNAL1! \0 ?/ h2 L& O7 c9 q2 @8 }9 {
3 VIA CLASS - INTERNAL2
& M- O, _7 V" K/ O2 z8 m1 X' s 4 VIA CLASS - BOTTOM
; e6 Z- a. e& ^9 S4 a' V6 i. ^4 z
( W2 [) l, R8 Z/ ~ WARNING: 63 data objects mapped to the UNUSED class were ignored.; e8 z- w" g9 i1 w3 w
===============================================================================2 s6 x/ n( \% s' W w
4 _6 a0 D# t2 MCreating E:\WORK\TEST\1.brd.
5 a$ w$ X: M/ j! O# F2 PLoading netlist:
$ H R8 n3 _2 l2 n6 W2 Q( t& lE:\WORK\TEST\1.TXT; m) F8 m2 ~/ H. Y& T: Y& _0 h
Writing database.+ E! J7 z+ P) o4 J8 F O
ERROR: Error while writing the Allegro database.- F- _# N) F# D6 G
Closing database.
* j# [. E* x& |Translation complete.
6 q5 N, i( Q( H8 z* V- L( T/ S" rFinished with errors!
* Y' s D4 \' j& m$ g |
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发表于 2011-10-12 00:37
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发表于 2011-10-13 13:23