PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
Basics of SI___________________________________________________________________5
, N4 T* |$ b& w6 i( g1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
, B( k. E6 u8 c7 Z+ r# G& i1.2.1 Waveform Voltage Accuracy _______________________________________5
2 V4 k% |' P* c! V1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
3 y: t- n. p' ?7 W, x5 c$ ?1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
6 ~/ F: C5 ?. ]4 s1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
; Z% J$ k8 u( N0 Y$ S# {1.5 RLC Transmission Line Model _________________________________________8
1.5.1 What is Impedance? ______________________________________________8
  Q" C8 |8 T! a7 [: Z1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

1 ^: J9 y& J" v4 K4 l) Q2.1.1 Summary______________________________________________________10
, O, E$ B) l8 G8 H2.2 Examples of dynamic interfacing problems _______________________________10
2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

7 P+ c: l$ x4 {/ P: {1 z0 M1 a3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
; v# ^" o1 }( ]1 I$ p3 F) P: `3.3 Receiver model_____________________________________________________21
8 o  ~3 c/ O& `6 B. B* i3.4 RC interconnection model ____________________________________________23
3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

, c% G1 A% ]) f4 w3 \2 c6 m4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
! n' K( _( s; F4.4 Critical Length _____________________________________________________34
! M/ s: o: W) y5 E4.5 Reference transmission line model______________________________________35
# z- p1 O1 y4 b1 l$ z0 c; G' ]4.6 Line driving _______________________________________________________36
4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

; q8 m/ R3 _7 |8 s5.1 Summary__________________________________________________________45
  n4 t0 G  i0 F: {6 }2 M0 ]# J5.2 Transmission time and skew___________________________________________45
9 [  M0 L6 N" Z# Y, z5.3 Effects of termination resistance _______________________________________46
5.4 Lattice diagram _____________________________________________________48
) f1 z7 A; y  o; N) h8 J" c8 I. }! s5.5 Examples of Real Lines ______________________________________________49
7 o2 C) ^+ m$ o, L2 u5.6 Simulation code ____________________________________________________51
( O9 K+ L9 N1 M5.7 Examples of results__________________________________________________54
5.8 Review questions ___________________________________________________55

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6 Design guide for interconnection ____________________________________________57

" p- Y; X. @: Q5 b. j2 W' G6.1 Summary__________________________________________________________57
# A/ O. E9 t. b6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
8 r: J! m- E- a6.4.1 Passive termination______________________________________________60
2 P- h9 Y8 }4 d. p0 Q. C7 }4 w6.4.2 Low power termination___________________________________________61
8 Z0 {; J5 U4 F6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
6.6 Driving bused lines __________________________________________________64
6.7 Design guidelines ___________________________________________________67
' o5 B$ P* ~# _% E9 z2 |9 k6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
7.1 Crosstalk __________________________________________________________70
) o9 k2 {& ^( O9 F2 M; d7.1.1 Summary______________________________________________________70
: \" V+ h; {, L7.2 Examples of signal integrity problems ___________________________________70
  l& Y( ~0 i: O8 F' N- S7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
) r& q( H# `# H, _7.5 Examples__________________________________________________________76
7.6 Near-end and Far-end crosstalk ________________________________________80
8 S# v* J4 l  M4 h: V3 W' I7.7 Review questions ___________________________________________________81


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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
( }2 n! N$ m+ e/ d8.2 Effects of Crosstalk __________________________________________________85
% K1 ]( e! j: C- `! \" H8.3 Passive countermeasures _____________________________________________86
  T" ]: q, i+ Y; _1 N7 ]8.4 Active Control of Crosstalk ___________________________________________92
# G4 C' Y0 D) Z( ?! M1 J8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
: Z" V2 p! i. A0 G' F2 {" j9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105

10 Design Guide for Ground & Power Distribution _____________________________107

10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata

0 P/ W# I) [5 J10.2 Decoupling Capacitors ______________________________________________107
10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
' I6 R- V& I  K% f10.5 Clock distribution __________________________________________________115
7 O8 K7 m5 p1 r10.6 Review Questions __________________________________________________118
11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
1 x- y4 Z- D* r* ]7 K11.2 Aim of the experience_______________________________________________120
; x. K! f' a+ b; s$ N11.3 Generator Parameters _______________________________________________122
5 f& j) I" Y1 ?11.4 Cable Parameters __________________________________________________123
5 W2 D2 f* q3 I! k1 x- t' f" x/ g11.5 Mismatch at driver and at termination __________________________________124
0 [7 X9 n" c& L2 `11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
9 |6 e1 Q& D& _' r4 G11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
5 e( S  A3 z$ g8 P' H* f, |12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
12.3.3
% v7 }6 N% {( l4 X3 }" ~9 [. hSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
12.3.4
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
9 v5 k+ a4 \8 @  }6 |) ^/ N12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
12.3.8
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
$ n5 I- P. C1 e6 @12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
- u* m6 l" Q  }% a: Y1 |5 v& k12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
# O* A& i9 F# \$ t: R! C12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata

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