|
本帖最后由 jacklee_47pn 于 2016-12-21 18:11 编辑
8 s' L2 V; A2 F+ C% M
% N8 d* }6 d# m) W% Z- a7 f來一個強悍的 PSoC® 4100 M-Series
+ s8 n3 f! g# e4 @! Z
$ i! V/ i' z) P5 x! S: X6 \32-bit MCU subsystem, |$ r4 p% z% d. l
24-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC
2 B( G/ q& V) J4 ]9 c Up to 128KB Flash and 16KB SRAM
' [# Y! q. W8 x1 P
& i5 Q' a$ I6 |9 bCapSense® with SmartSense™ Auto-tuning' x; Z' j* N8 R# o b8 v# f8 a
Cypress Capacitive Sigma-Delta™ (CSD) controller" p4 n" @3 w( v! i! j
CapSense supported on up to 55 pins% z1 d1 y. m; ~
) d, ]( j9 ?# @1 K( G K; {Programmable Analog Blocks
6 V# \$ V O1 M p8 D* B" { Two comparators (CMP)
3 ^& [2 y5 K: H5 f& o Four opamps, programmed as PGAs, CMPs, filters, etc.
+ p" y. |1 h' y One 12-bit, 1-Msps SAR1 ADC1 ?7 h! y, l: P5 H, E8 u" C& p
Four IDACs2 (2x 8-bit, 2x 7-bit)0 m; d3 H- L6 y* a6 e2 m; Q: C
6 x3 B! [$ ~4 s9 q
Programmable Digital Blocks
5 W6 u" }, l1 ~; G2 B0 E: O* U Eight programmable 16-bit TCPWM3 blocks
6 B' }+ v/ Z s# c Four SCBs4 : I2C master or slave, SPI master or slave, or UART
0 ^ d- c; p' I% l" S% Y: v' {
, V5 `4 j6 I9 C! ?- T5 R5 M `Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),64-pin TQFP (0.5-mm pitch), 68-pin QFN4 B8 U- c, m. i( e9 s; }
|
|