我用cadence16.5 ConceptHDL设计原理图,完成后道pCB,我使用的Top-down式原理图设计方式9 d) g/ d- J; w& d) Q8 H: ^
导PCB时提示“Connectitivity server is unable to load design. The .xcon file might be missing or incorrect. Your design needs to be netlisted in 16.4 or later version of Design Entry HDL" $ K, R0 g; n) |# [" I, e - \3 ^' U2 p8 N" A这个是由什么问题导致的?6 i& w1 a- T, ]3 O6 ~9 w; [; c