Hotfix_SPB16.60.022_wint_1of1

steven.ning

http://pan.baidu.com/s/1bnpaZfD

steven.ning

yuxifeng 发表于 2014-2-11 10:38
8 i0 B% |- e5 D, g9 @能告知补丁包的功能及解决的BUG吗？

DATE: 02-07-2014   HOTFIX VERSION: 022
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, p) v' s' k1 i+ x* W7 LCCRID  PRODUCT        PRODUCTLEVEL2   TITLE
% Z8 `( \! I( R- b) @* I- A===================================================================================================================================
4 }% ]: R  m) b: Z192358 ALLEGRO_EDITOR PADS_IN         Pad_in does not translate some copper shapes
! J3 `" t7 c* @7 ?& n: U- e' I' i$ I: a222141 ALLEGRO_EDITOR PADS_IN          PADS_IN: Extra shapes are created whenimporting PADS design
274314 ALLEGRO_EDITOR PADS_IN         PAD_in boundary defined for flooded area be translated DYN
) C$ o& @  T; p413919 ALLEGRO_EDITOR PADS_IN         pads_in cannot import width of refdes.
/ E( |& y2 |5 H' ^. M609053 ALLEGRO_EDITOR PADS_IN         "Mils to oversize" of "pads in" did not workcorrectly for MM data.
, [- ~$ ~! {: p5 d666214 CONCEPT_HDL    OTHER            Option to increase Line thicknessin publishpdf utility
738482 ALLEGRO_EDITOR GRAPHICS        Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
: g/ ^5 q; g2 X: q982950 CONCEPT_HDL    OTHER            change the mouse button for thestroke to have same function with in pcb editor
; f  c2 u6 {- s1020886 SIP_LAYOUT     LEFDEF_IF        a quicker way to promote die pins (byimporting macro_pin list)
1032678 CIS            VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.
1033864 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translates teardropspresent in design
1054862 CONCEPT_HDL    OTHER           Option to increase Linethickness in publishpdf utility
$ ~8 Q3 ?5 }$ C* W" H0 ?9 ~* X1055252 FSP            PROCESS          Add a synthesis option to target agroup to contiguous or consecutive banks
( t3 e% n8 J! {* n2 P* {. F1100772 CONSTRAINT_MGR OTHER            In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.
1135020 CIS            DESIGN_VARIANT   Variant list is showing wrong results forhierarchical designs
1138951 SIP_LAYOUT     DIE_ABSTRACT_IF  Fix die abstract r/w to properly supportpinnumbers on ports
/ O9 t( V, [5 L1140042 CONSTRAINT_MGR OTHER            Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
1143662 ALLEGRO_EDITOR INTERACTIV       Enhancement Request for RMB - Snap Pickto  options increased to include Pin edge
$ v3 |% X* H) f6 b1147961 PSPICE         SIMULATOR        Simulation produces no output data
1150874 ALLEGRO_EDITOR PADS_IN          Dimensions in PADS are not translatedcorrectly during pads_in translation
0 q2 A9 S  r4 C6 O1154184 CONSTRAINT_MGR CONCEPT_HDL      Difference in the way topology isextracted in 16.3 versus 16.6
1154770 CAPTURE        PROPERTY_EDITOR  Variant Name property doesn't show value inVariant View mode
0 U3 P# ^6 d( _! Z2 |1158350 CONCEPT_HDL    CORE             Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
1162347 ALLEGRO_EDITOR EDIT_ETCH        Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly
1165553 ALLEGRO_EDITOR INTERACTIV       Subclass list invoked from the statuswindow does not represent correct colors.
1168079 FSP            MODEL_EDITOR     Clicking OK or Save As in rules editorallows user to overwrite the master with no warning
. m  E- k$ Q4 ~/ y2 j1172043 SCM            OTHER            : in pin name causes SCM to crash
1172207 CAPTURE        STABILITY        Capture crash while adding new partfrom Spreadsheet
) u" n. U3 X, l! z2 M' H# U! w1172743 ADW            TDA              Allowed character set for thecheck-in comments is too limited
1174099 SIP_LAYOUT     WIREBOND         Option to reconnect wire based on 縫in name� in the Wire Bond Replace
/ Q% |. i( ^8 F+ _4 l2 T1177672 APD            IMPORT_DATA      Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process
. [( t* s2 {# G5 n" @1177714 CONCEPT_HDL    RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible
9 I! P4 M) z5 X- U9 s* [3 r1177820 CONSTRAINT_MGR INTERACTIV       Done the Allegro command when attemptingto launch CM
1178586 ALLEGRO_EDITOR EDIT_SHAPE       Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD
4 P9 e0 q$ }3 o. v* g1 o/ K1179688 PSPICE         STABILITY        pspice crash for particular HOMEvariable vlaue
1179827 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
4 D* p" I, }. d$ G5 k- Z( K1179879 SIP_LAYOUT     STREAM_IF        Data file corrupt when exporting Streamdata from SiP database.
1180164 F2B            BOM              BOM csv data format converts toexcel formats
1180477 ALLEGRO_EDITOR INTERFACES       IPC-356 output is listing a duplicatelocation in the comment section
+ [! Q/ [$ O( Z0 D1 `& R6 O1180932 SIP_LAYOUT     OTHER            SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet
1181377 ALLEGRO_EDITOR INTERACTIV       Pick Releative does not work correctlywith RMB-Move Vertex
9 |+ S2 Z2 _, l  S4 f1 \* u1181516 ALLEGRO_EDITOR DRC_CONSTR       Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.
7 P2 L; }# `0 L+ L8 E* q/ c1181739 GRE            CORE             Running Plan > Spatial crashesGRE
1181935 ALLEGRO_EDITOR DATABASE         Enh. Property that allows internal C-CDRC errors
1182185 SIP_LAYOUT     OTHER            SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
; _% H9 h9 f' T; v( _1182566 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap
1182599 CONSTRAINT_MGR DATABASE         CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.
6 A3 u- E2 ?5 Y" f( e1 [/ s1182892 CAPTURE        SCHEMATIC_EDITOR Pspice marker rotationbefore placement
1183682 ALLEGRO_EDITOR DRC_CONSTR       Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
4 C6 L, T% I" n/ M2 ^. K& L1185445 SIP_LAYOUT     DIE_ABSTRACT_IF  Die abstract export needs to be able toselect xda file type when browsing
1185932 ALLEGRO_EDITOR SHAPE            Soldermask in solder mask void DRC
1185946 CONCEPT_HDL    CORE             Ericsson perfomance testing report5 sept 2013
1187213 FLOWS          PROJMGR          Unable to lock the directive:backannotate_forward
1187444 ALLEGRO_EDITOR DRC_CONSTR       With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
5 U. Z9 W8 `! B& ^2 }- T( n1187597 ALLEGRO_EDITOR DRC_CONSTR       No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.
) U0 K; x1 b/ I1187723 FSP            PROCESS          Synthesis can fail depending on componentplacement
1188164 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
% w- {/ O- i7 V( R) ?0 Q1188245 CONCEPT_HDL    CORE             INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
" \( {  L9 m! E  J# I1 j  B! e1190927 CONCEPT_HDL    CORE             Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
8 d; O2 s7 V$ {. V3 k" R1191497 ALLEGRO_EDITOR INTERACTIV       ENH: Adding names to the text blockparameters numbers
' Q1 _$ Z7 y' `. r" m1192005 SIP_LAYOUT     IMPORT_DATA      Import SPD2 is missing 1 smart metalshape from file
( |$ ~) T: C* d% f7 ^6 @% |8 Q  X1192204 ALLEGRO_EDITOR EXTRACT          Need ability to extract vias that arelabeled as microvia
2 t. Z9 X# v" W3 j1193063 ALLEGRO_EDITOR MANUFACT         TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
1193418 ALLEGRO_EDITOR GRAPHICS         3D Viewer can`t export image  in both SPB166S015 and SPB165S047
1194305 SIP_LAYOUT     EXPORT_DATA      export package overlay creates file withno package info
: U! l) j; g  H7 H3 x1 Y1 S1194418 APD            IMPORT_DATA      issue when doFile->import->netlist-in wizard
, p" e  k( {1 Q2 G. q1195279 F2B            PACKAGERXL       Ptf files are not being read whenpackaging with Cache
8 D8 ~  x3 h! v, D& e. T7 s1195374 ALLEGRO_EDITOR INTERACTIV       Modules are not showing up in Tools >Module reports
; @- z. t! F% B, E6 t" {1196603 SIP_LAYOUT     EXPORT_DATA      Change form for "Write PackageOverlay..." to better support longer lists of routing layers
; R% j7 ~' O! \+ \1197302 CONSTRAINT_MGR UI_FORMS         Inconsistancy in selection of objectfor Spacing Constraint Worksheet
% l8 @- o8 C% g+ F1197399 CAPTURE        OTHER            Draw toolbar disappears when usingPrint Preview
1197543 ADW            TDA              TDO does not correctly showdeleted pages
1198033 CONCEPT_HDL    CORE             Signals do not get highlightedwhen Show Physical Net Name is option enabled
$ c& _- q" q8 ^4 d" a1198468 ALLEGRO_EDITOR GRAPHICS         3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
* t* U9 c. d; F2 T* y2 d! S1198617 CIS            GEN_BOM          Mech parts are showing with Partreference in CIS BOM
1199764 ALLEGRO_EDITOR SHAPE            Allegro crashes when trying todelete small island on POWER layer.
7 q+ d: v  ?1 g1200232 ALLEGRO_EDITOR INTERACTIV       Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.
1200748 ALLEGRO_EDITOR INTERACTIV       Additional pin edge vertex object tosnap pick
6 ?- E$ ~. s6 \) U4 l- k1201056 ALLEGRO_EDITOR DATABASE         Unsupported functionality strip designcreates a .SAV file
1201638 CIS            PART_MANAGER     Part retains previous linking inside thesubgroup
3 g3 v! Z4 l1 K) x! g1201834 ALLEGRO_EDITOR PLOTTING         Bug: Import Logo command changesresulting imported object
1202406 SIP_LAYOUT     OTHER            enable the dynamic display of componentpin names for co-design dies in Sip Layout
8 q0 _# D; _- J7 ]" I7 {1202431 CONCEPT_HDL    PDF              The publishpdf -variant optionshould have a "no graphics" option
' j( p# Q% O- O1202717 ALLEGRO_EDITOR DATABASE         About Warning(SPMHA1-108):Illegal linesegment ... end points.
" O  Q3 P' v& K2 g4 I7 S9 y; U5 [1203459 CONSTRAINT_MGR INTERACTIV       Object Report has no mechanism to outputinformation for a specific design.
( i: |  [7 n) n5 T1204544 F2B            DESIGNVARI       Variant Editor does not warn on save ifno write permissions are on the file
1205500 FSP            CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax
  w) s: {1 T7 @/ G1205952 ALLEGRO_EDITOR GRAPHICS         Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
1206103 SIP_LAYOUT     IC_IO_EDITING    add port name property to pins, and addSkill access I/O driver cell data
5 D4 i$ |& U* ~- b9 p' Q# Y1206546 CAPTURE        ANNOTATE         User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�
7 \# x: a" }* s% O1206561 ALLEGRO_EDITOR GRAPHICS         Not all mechanical symbols made with Stepfiles are displayed in the 3D View
1207125 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECSet mapping wrong for 2 bit in a 4bit bus
1207386 CAPTURE        GENERATE_PART    Altera pin file not generating the partproperly
1207629 CAPTURE        TCL_INTERFACE    Bug: GetMACAddresses tcl command notworking
1207994 CAPTURE        TCL_INTERFACE    TCL pdf export in 16.6 fills DOT type pinswith black color
1208017 F2B            DESIGNVARI       sch name is not same when updatingSchematic View while backannotating Variant
/ W% S0 O3 E5 T' {4 M, S" L1 ^1209363 ALLEGRO_EDITOR INTERFACES       When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
. `. y! B2 Q" `; ~4 y; d9 w: ]1209769 CONCEPT_HDL    CORE             Top DCF gate information missing
9 I9 W, [! i+ y1210194 CONCEPT_HDL    CONSTRAINT_MGR   HDL crashes with Edit Via List dialog box
3 Z; v  g& L$ P, y. h1210442 CONCEPT_HDL    INFRA            Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
1210685 ASI_PI         GUI              User can't edit padstack inPowerDC-lite
$ O; J. J+ E$ D* t1210744 SIG_INTEGRITY  SIGWAVE          SigWave: FFT Mode Display unit seemsnot to be correct
1210829 CAPTURE        NETLIST_VERILOG  Shorted port is missing from verilog file
1210850 CONCEPT_HDL    CORE             DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library
0 }: i1 p8 Z$ g% z8 @1 Y' T$ k3 [1211620 ADW            COMPONENT_BROWSE Component BrowserPerformance
, j8 `: V. D0 w7 C7 _& O1212102 ALLEGRO_EDITOR INTERACTIV       Shape edit boundary adds arc mirrored tothe highlighted preview.
* F& G* |9 l0 a# Y+ u5 \1213294 CONCEPT_HDL    SECTION          DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
* O) F% u: x8 c7 m2 m1213402 APD            DATABASE         The old "ix 0 0" fix  is now causing the features to lose netsentirely.
1213694 ALLEGRO_EDITOR PARTITION        Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition
6 B4 [( @  k4 L- ]1214247 CONSTRAINT_MGR UI_FORMS         Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting
: i8 g+ i; P8 V1214320 SIG_INTEGRITY  SIGNOISE         signoise command with -L and -k option
1214433 CONCEPT_HDL    CORE             Genview does not update sym_1 withports added to the schematic
* H. q1 a/ b) o- q" n. t3 j1214909 ALLEGRO_EDITOR NC               NC Drill Legend show extra rowsfor drills
4 Z) e' v8 @% Q8 A- Q0 [) N! e9 M$ j1214916 SIP_LAYOUT     OTHER            package design integrity check forvia-pin alignment with fix enabled hangs
$ ?! G; k# k2 d, X* ~. d5 I1215954 SIG_INTEGRITY  SIMULATION       Cycle.msm does not exist error whensimulating extracted net
1216328 CAPTURE        STABILITY        Capture crash
7 v6 C, ]/ c' x8 h% S1216993 ALLEGRO_EDITOR DRC_TIMING_CHK   Allegro crash on SPB16.50.049
1217450 F2B            BOM              ERROR 233: Output file path doesnot exist
6 T" e! b/ ^( h1217612 ALLEGRO_EDITOR INTERACTIV       Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37
2 Q# F' [6 u! g* o, v4 C& A1217823 ALLEGRO_EDITOR INTERACTIV       Compose shape fails with SPMHIS-473
1217887 ALLEGRO_EDITOR INTERFACES       An undo option to be made available inthe STEP Package Mapping window
1218665 ALLEGRO_EDITOR INTERFACES       In step viewer, the bottom side partsare placed above the pcb board surface
! Q! }6 g! M, P( b2 K1219053 PSPICE         PROBE            PSpice crash with the attachedDesign
1219067 ALLEGRO_EDITOR EDIT_ETCH        dynamic fillets behavior is unstable
1219095 ALLEGRO_EDITOR MANUFACT         Design Cross section chart is taperedfor two layer board
1219126 ALLEGRO_EDITOR SKILL            Skill issue with axlRefreshSymbol()
+ b, ^! T& g1 d8 ^% v& ]1220701 ALLEGRO_EDITOR INTERACTIV       View > Windows > Worldview(showhide view command) fails with command not found
1221057 ALLEGRO_EDITOR REPORTS          Units in Cross section report forspacing is not synced with the design
9 L: [5 V% A! C% c2 G% R4 d4 e( l1221139 ALLEGRO_EDITOR EDIT_ETCH        Delay tune is not tuning differentialpair
1221157 SIP_LAYOUT     IMPORT_DATA      import spd2/na2 file is not importingdata correctly into sip
1221163 SIG_INTEGRITY  GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.
1221416 ALLEGRO_EDITOR DATABASE         strip design for function type
1221931 ALLEGRO_EDITOR DATABASE         Fatal software error when embeddingcomponent
% U) W/ d0 C) d3 D1222105 CONCEPT_HDL    CORE             Moving Pins around the edge of aBlock causes the text of the pin to change its text size.
1222124 APD            DATABASE         Same Net DRC's exhibiting inconsistentbehavior.
9 y- L% o% @: \/ h, h: ], M( q1222272 SIG_EXPLORER   EXTRACTTOP       Cannot extract net or open SigXplorerafter selecting a netgroup
$ l' B; p) u0 U$ {2 b1 C1222329 ALLEGRO_EDITOR SHAPE            STEP-Model  Symbol which has place bound bottom is on Top
1223183 SIP_LAYOUT     BGA_GENERATOR    Getting an incorrect error message whenusing the BGA generator with a long BGA name.
5 `% c0 V0 U* d8 b1223662 ALLEGRO_EDITOR REFRESH          Allegro crashes when trying torefresh symbol
* G) V0 u* k& H* O  O6 [9 X- k1223932 CONCEPT_HDL    CORE             DEHDL block desend does not find1st page if its not page1
4 `; Q: [9 @: w+ h- B4 X8 f5 Q+ N1223940 CONSTRAINT_MGR UI_FORMS         Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.
  k' F/ O+ W- }% k8 Y( I' O5 ?% E3 t1224127 SIG_INTEGRITY  IRDROP           Is the old static IRDrop in 16.6officially supported?
1225492 PCB_LIBRARIAN  CORE             PDV expand vector pins resizessymbol outline to maximum height again
) P9 h5 d& j; j3 k* T, A* Y& o' i1225546 CONSTRAINT_MGR ECS_APPLY        nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
1226405 ALLEGRO_EDITOR INTERFACES       File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder
1226448 PDN_ANALYSIS   PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
1228721 SIP_LAYOUT     OTHER            File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer

steven.ning

wolf343105 发表于 2014-2-11 15:15
3 F( X; ^( \& k( s非常感谢steven.ning,祝你马年发大财.

, {# r' m  r1 Q0 t$ E: y# x( t4 ]9 R: p谢谢，也祝你马年行大运！

nbxiong

等的花都谢了，更新好慢，跟看美剧似的。。。

wolf343105

非常感谢steven.ning,祝你马年发大财.

jsf120

找了半天，感谢分享

steven.ning

yuxifeng 发表于 2014-2-11 10:38
! ]4 G, E7 _8 l4 @1 J3 r1 i能告知补丁包的功能及解决的BUG吗？

我只是从EDA365网上搬运了一下而已，原来那个下载太慢，我把我下的转到云盘上,速度快，方便大家下载.更新了什么我也不清楚.

yuxifeng

能告知补丁包的功能及解决的BUG吗？

suiwinder

正在下载

sztyzhi

太快了，刚装了021