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8 K; d' |5 | o' A7 ^DATE: 02-07-2014 HOTFIX VERSION: 0222 K: J# u- h1 j/ ?0 n
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CCRID PRODUCT PRODUCTLEVEL2 TITLE- \( h( n" W5 |7 m2 j: x4 f: g
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) ?, ^8 J& W6 z, _8 }5 u3 @192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
) [/ H3 [) D* b# a6 g222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design* {' p* L& L' c$ @$ S+ H5 n+ h
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
4 v$ N f& E2 }: \) D6 S6 d5 Z' s: v413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
* l8 ?2 \" z8 Q$ @& H' \( g609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.; \1 a* p' Y- x5 B i# X; {
666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility
( L, g) {2 D# ^9 y+ J, ^738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard% B6 V% D. e# J' T
982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor, J3 Z' ?7 \$ @4 a' o6 w
1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list)
: v; g# t) N3 t* s1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.
9 h% `- R- Q5 c2 ^- E0 x* n; Y8 I7 e1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design
x: A% r1 a' x/ P: @9 F1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility
. ^3 ^5 n& r9 ]* G) b5 J1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks
3 s" L6 Z& A3 t p4 @1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.+ n+ v, [) I0 Y& J: b/ Y; [
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs
+ ^- x' Y4 \- |7 h$ a9 h1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports9 V% f; @" J/ F8 i& h% U
1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
8 W" O8 k- |# }% @+ s- N7 Y1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge
1 R% b8 P/ `7 C* B5 M1147961 PSPICE SIMULATOR Simulation produces no output data/ R3 J$ i9 ^. t% o+ @# ?- D
1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation: @' ], D+ w$ e# G, g2 S
1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.6' G/ b' D/ x6 L5 q+ N- P
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode
* @* X9 ~3 C1 M3 ]* V1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
3 Y; ^/ Y2 t% _4 N$ H- u/ W2 h1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly
& J+ p! C3 V4 L% E5 E/ c/ c$ F1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.; B2 [) {/ Y3 y: T8 i% J
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning7 W1 E. K$ y5 K; \
1172043 SCM OTHER : in pin name causes SCM to crash
) n/ H) `: t& S ]# q/ _1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet
1 J0 Y: I# C" ^, x( E9 z; N1172743 ADW TDA Allowed character set for thecheck-in comments is too limited
0 N' \" h6 i2 S% d0 a1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
6 A* y# E! f! s1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process& Q5 u. D1 `9 J6 r' m: u; `( h
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible
( e" g- w3 m, z3 |1 q& `, P1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM7 \" q1 o: F% F% H' A( j( A2 Y
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD- p1 L2 u9 X: r* d" R5 d6 Y
1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue+ w9 O: r- y% y+ |5 R
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
1 V7 O. p+ Z0 k; u5 R1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.* t5 a; i1 v7 E. F: q; T6 K- z5 i( b+ v
1180164 F2B BOM BOM csv data format converts toexcel formats
! e" \. n- U1 k1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section
% `" K6 C T; S! N* |% Z0 J1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet
" ~. Q9 R* e% A2 }, W+ m1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex( }" A' e0 q# S) S7 {- r0 z
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.
3 z5 x1 N( p+ _: d* S5 j& U& l# K1181739 GRE CORE Running Plan > Spatial crashesGRE
; R$ H4 q; Y" e- \5 v4 j# W1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors7 E$ |- a* `- c* {# U w
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
1 d+ E9 s6 u+ ~: m1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap6 h- X/ I" `' r* J# W
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.1 h7 {5 o3 I; z5 K8 @
1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement3 j; ?. u+ M2 u+ U
1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
7 c5 W/ q# L3 R( w1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing
+ g8 n; f4 O& R: W8 i$ ~1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC
3 J% R. z+ j# U1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013
) E" Y6 l0 e! V1 I1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward
* {) _6 o4 S. I7 M: \1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
' v' k$ D. ]2 Q5 K' t1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.% P5 \3 o; I6 I* d1 n' K. @
1187723 FSP PROCESS Synthesis can fail depending on componentplacement. H* d: M |+ v1 X f9 v( e3 @
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP$ f( h. S7 T% g( P# ^0 {
1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
: q+ V# l" o; a% C. Z. b1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
* g j. W- N" F9 E7 R. u0 M% P1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers+ i4 K* ?" J# y# `6 E! Q
1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file
& b+ z s7 F0 Q+ b3 G' G3 c1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia
6 B' Y4 [3 \( Y) w1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
! a( X6 j& B& X4 L8 z$ r1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
) w( }9 E. K) |' b+ j6 O! M1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info
, W; q2 {; V: u7 x% \( Q7 M% f* B+ y2 d1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard0 t% D; f; W. k* A
1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache$ ~( B$ a6 Q! I5 g5 O
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports
! ^8 A8 _5 j% ]0 Q" f5 r1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers; S8 Q. u9 S8 X& B4 k8 H
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet
) g: q1 ?/ v0 q( B; R- y1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview
5 J. @# [3 K8 P/ c1197543 ADW TDA TDO does not correctly showdeleted pages
$ i& P0 _8 Y7 q, F1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled; R" o! R* V9 k- G& ^+ ]3 c0 V% C8 ~
1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
8 J; N/ p) q: [5 T. o7 T1 C1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM, i5 Y0 F! \; y# \$ G \
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.
8 V! i: _7 s- V% g7 i1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.9 b' C) X$ A" [8 B3 i( G
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick; M! v4 l4 A0 r+ i. y0 m
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file
% D3 f( m, A( h9 I0 w3 m8 c1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup
, {: B5 e w1 A) \- r1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object1 y u+ X5 K: l7 T5 ^
1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout% E, P) l# a' H P' w( v
1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option9 Z. B) ~3 `( H
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.
+ }: `% s1 P. d$ }2 z+ p! K# @- p1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design.
: C0 n( S* s) C' y1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file1 | H. c6 X# t6 |
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax
; u P& X1 w! g* I7 c1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled8 p& s& H: z6 J
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data
: l/ M9 ?- e# p# E7 Q1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�
' `5 }' k5 F; g7 F, B, P1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View
1 v& V8 O" Y- W" U, r1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus5 B; V4 ^& ?$ I) h2 S A
1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly- q2 ?8 |3 t+ s2 H
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking
$ y5 Q/ x- k- W3 S, D" S0 E& K1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color& N6 D f: b9 v% n
1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant
8 ~( s6 W* S! h7 V/ j( \. _ o; U1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
6 n: Y; Q/ ^! k+ ?1209769 CONCEPT_HDL CORE Top DCF gate information missing$ H# o5 h9 S" t! }
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box4 E) N' O7 W q; C! e4 R5 N: l
1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
! m; r) i# q+ j1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite5 M" \/ C8 k9 I9 P1 @- h
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct
" V) R. |, }: q: O' {5 b1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
: _" k4 w( Y1 U9 v5 Q/ D1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library- ~. T- U! U# q6 U2 {4 E
1211620 ADW COMPONENT_BROWSE Component BrowserPerformance4 i" P3 O" k; n/ V* @
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.
1 s- U1 J$ `! a6 \ B* f8 P# `3 y8 E1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
# Q2 G! A- i" H& I7 j4 Y1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.& s2 x# s! t4 \
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition
; Q1 K. q7 j' \1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting( B u; L- F5 ?) v. U
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option
1 C/ o: E; w' r1 q6 D9 q& z X5 c- F1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic
1 t4 ? L' E# s! ^2 R9 g1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills
. N& c5 O8 i3 h/ `* E- n1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs) Y) E; y/ H, M3 O3 t( e, i
1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net. a$ v2 ~) T1 |: B
1216328 CAPTURE STABILITY Capture crash
) B4 m# N( D' z8 s4 {1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049
, [* d) A) ?5 H& J0 X1217450 F2B BOM ERROR 233: Output file path doesnot exist
) o9 ?( F) S) \5 k, \" T# y; `1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37
* @* }: c0 @( I5 V- H1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473
" X$ @) ?# i* r1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window/ X3 E0 n7 T4 y5 t& T0 s" u
1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface+ X) Z/ m3 Q: c/ U
1219053 PSPICE PROBE PSpice crash with the attachedDesign
& _2 w$ y' i. P! q% _% b. e {' [2 G1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable
3 s$ v x9 H2 D1 c- P. a1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board: o |6 ?& W* _2 N @, I6 X' x
1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
! |: ?6 ?( q, m) @ x4 e1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found8 ~" t2 u0 K9 s( Y6 U. V
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design
( {+ s0 {1 h' b$ Z& V1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair
) _ b* S1 ?5 b) {: X$ x1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip) p* t8 W; W1 l2 [+ J
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.
8 d" p. [! W& b1221416 ALLEGRO_EDITOR DATABASE strip design for function type( s; o# O: M O! z/ w
1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent5 g6 t" x" h) ^0 m7 ]/ @. A3 L
1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size. \# A$ u( P8 ?* ]
1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior.
7 q" o! ? M+ @! d5 J1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup$ S" e& X& A( N1 ?/ E$ K) K
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top' O% D& e) q3 v' ?; Y
1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.
& R9 }( l) m/ n$ S o1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol
6 e% B& a; J! d& }+ q1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page1& i/ o; e; G9 \. @& S y9 N+ I; ?
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.& A' Y$ U+ c$ c* g+ `
1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?
$ \, H1 }3 ?2 j1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again
0 j2 p- x9 f- ^1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end! Z' ~; a1 h4 |+ k8 v' f0 _
1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder6 h1 W- P$ y# [+ f; n
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL H0 U& {) N4 v: H
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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