|
|
2#
楼主 |
发表于 2013-10-29 17:11
|
只看该作者
8 u8 I, u0 g9 i7 K' W
DATE: 10-25-2013 HOTFIX VERSION: 018: V7 {) U) u# \4 p. F% K- L
===================================================================================================================================
/ j$ @) V; \7 G9 T" i- y% K1 aCCRID PRODUCT PRODUCTLEVEL2 TITLE$ R! K& u* x9 g- {; x t1 c: e
===================================================================================================================================
* A3 b8 R) ~+ N5 m5 n! V6 z1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefinedefault units in HDL
- U: a! t+ M3 i, v1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapesand text that are not part of the design with opengl4 O2 F* j% I# o
1176990 CONCEPT_HDL OTHER DEHDL BOM tooldoesn縯 see similar names.
: A: I% v8 p# x- ^. d2 R% }& Y1179665 GRE CORE Plan TopologicalCrashes after around 8 hours of routing.
% h" C E' B9 t4 L* J7 c) w1188193 CONCEPT_HDL CHECKPLUS CheckPlus notrecognizing PIN as a base object.( H6 u0 J9 h" e5 o
1189100 SCM OTHER Replace part inSCM using ADW as library fails5 V8 ?. x) V) K6 w, Y% a6 N) x0 D4 h! Z
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preservemode.
5 U: k, I& o9 U" ^1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes localobjects in other blocks
7 f. g# q) N" V; H1194597 FSP OTHER Pin definitionproblem
6 P) t9 o# S; K0 b' |1195202 SIP_LAYOUT LEFDEF_IF Cannot add .leffiles in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
4 l( p& M0 l4 d1195309 GRE CORE GRE crashingduring Plan Spatial.
- E# }; ?# ]4 q9 A7 Z6 R1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol isplaced w.r.t. board origin and angle is blank
* Y7 ]: m, Q9 T+ L3 O/ ]1198521 CONCEPT_HDL OTHER Cadence DEHDLissue - Note for Hotfix_SPB16.60.016_wint_1of11 D! T/ y1 Q( n( ?6 I" I) ^( z/ g& z
1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which usesPLACE_BOUND layer for any symbols that do not have STEP model mapped
- ^' w* }9 v0 J0 h% b* C1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant whilecreating pcb editor netlist. |, v7 S# D* `, f+ Z
1199323 GRE IFP_INTERACTIVE Crash whenimporting logic
- a6 m, b& n0 h3 X. \' d+ q2 M1199368 SIP_LAYOUT DIE_EDITOR Refresh of dieabstract in die editor with this design takes over two hours
8 [. u% r- x( E7 O0 R( p1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Toplayer |
|
[复制链接]
/1 
发表于 2013-10-29 17:10
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
发表于 2013-10-29 22:30
