菜鸟求组:仿真multi-threshold cmos,实现NAND gate

ak11112222ak

source 总是出现以下问题，描述的时候已经说了是接地的了啊，为什么还是会当作断开的呢？
Circuit: *Main mtcoms file
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; T+ B% b$ c% \; w) d* d/ i9 p( Z, lWarning: There are nodes with less than 2 connections.
9 r2 |. b& n% WThe table of nodes with less than 2 connections is generated after sourcing...


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***warning***: the following singular supplies were terminated to 1 meg resistor
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supply       node1            node2
vdd           vdd                  0
v1           a                  0
1 d6 u; i; K' v4 q0 _2 Jv2           b                  0
0 Y- M* ?$ P# P' k) U. [( {. fv3           sl                  0


7 s. W- u+ L1 j' u5 mThe following nodes have less than 2 connections:
-------------------------------------------------------------------------------------
| sl                 | b                  | a                  | vdd                |
-------------------------------------------------------------------------------------
+ L1 [- r- u7 U+ p: u4 y4 B, I! s; o一个描述netlist的文件：


0 G1 \" T$ Z8 c: G7 u  |8 B* SPICE export by:  S-Edit 15.13
( m9 @$ _1 B$ m0 b* Export time:      Tue Jun 12 11:15:52 2012
* Design:           mtcoms
* Cell:             Cell0
* Interface:        VResistor
* View:             VResistor
: X& Q2 O# T, v$ G& n; b* View type:        connectivity
* Export as:        top-level cell
9 J7 ?) Y5 v) B, |/ z* Export mode:      hierarchical
* Exclude empty cells: no
( ]. b  }, U% u, j* Exclude .model:   yes
3 x- ~8 ]9 v& @2 c" i# q! n* Exclude .end:     no
* Exclude simulator commands:     no
* Expand paths:     yes
- b& X) T9 |0 _5 Y4 N& c1 x) m9 X0 r: L5 Q* Wrap lines:       80 characters
- l: h- A2 s4 t' A5 f* Root path:        \\en-file\users\houx\Profile\Desktop\ankun_dong hw2\mtcoms
* Exclude global pins:   no
* Exclude instance locations: no
* Control property name: SPICE
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********* Simulation Settings - General Section *********
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*************** Subcircuits *****************
" m. i' N4 r# E.subckt INV A Out Gnd Vdd  
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" `) ?  z$ Y' K' Z. Y4 I/ o  d*-------- Devices With SPICE.ORDER < 0.0  --------
) \% I+ {, F- _* Design: LogicGates / Cell: INV / View: Main / Page:
2 D5 k6 `) W8 {6 \% C5 `' P7 H* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
6 ~6 @0 _4 x$ c4 M* Date: 06/13/07 16:17:11
* Revision: 3 $ $x=7600 $y=600 $w=3600 $h=1200
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) y; A, _9 U. P# |6 ?*-------- Devices With SPICE.ORDER > 0.0  --------
. M( A  b' R# Z5 m& nMN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=4600 $y=2600
' J( L2 O4 G& Q# `) h+$w=400 $h=600
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u $
& n, ?2 N4 P6 j; j0 j2 X0 `+$x=4600 $y=3600 $w=400 $h=600
1 t0 s% @  M- R5 u' f.ends

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*-------- Devices With SPICE.ORDER == 0.0  --------
***** Top Level *****
) N. a& _% L  c$ w+ w: \XINV_1 SL N_2 Gnd Vdd INV $ $x=350 $y=-2300 $w=900 $h=600

*-------- Devices With SPICE.ORDER > 0.0  --------
CCapacitor_1 VDDV Gnd  1p $ $x=3100 $y=-400 $w=400 $h=600
CCapacitor_2 GNDV Gnd  1p $ $x=3100 $y=-2500 $w=400 $h=600
MNMOS_1 Out A N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
  N( \, w: G: B! N4 A- R- q$ o! q+$y=-800 $w=400 $h=600
- X# H0 Q5 f! o6 X- r0 {MNMOS_2 N_1 B GNDV GNDV NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=-1500 $w=400 $h=600
7 q) Z; i8 I% ?+ W: ]( h) AMNMOS_3 GNDV N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
+$x=1100 $y=-2300 $w=400 $h=600
MPMOS_1 Out A VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=300
; Q+ f& c- z5 {. }4 G+$y=-200 $w=400 $h=600
- }  h3 K( `1 }# k; o  W1 rMPMOS_2 Out B VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1900
; Q$ N# c- X* ?- e7 ?* [# L  ?+$y=-200 $w=400 $h=600
% x' F, k6 ~& P* A5 B8 o6 lMPMOS_3 VDDV SL Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=700 $w=400 $h=600
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********* Simulation Settings - Analysis Section *********
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* c  h4 s6 B$ P9 x; O********* Simulation Settings - Additional SPICE Commands *********
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/ ^. p" Y# j$ G5 x; s: w* z.end
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icy88

source接地的描述应该是 vdd vdd 0 0,你后面少个电压的值