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Translating E:\WORK\TEST\1.asc.; |3 i+ T' D8 q; V
Reading PADS ASCII file header.
4 {) H* g. U1 h& o: {! j4 H Version = PowerPCB5.0
+ p3 ?* ~" `& {9 B* Y& c5 q Route Layers = 4
, ?5 R- o, c: X* H- V Units = METRIC
$ H( X* r9 z; w Hatch mode = Vertical / Horizontal q m: m, \" \
Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.000315* l0 }. \7 l- m/ B8 P3 e
Initializing new database.
1 y; w# B+ t- C Creating layers.
' u" U0 f* l* dReading PADS ASCII file body.
8 n. s4 j; ~5 K) m, Y *PARTTYPE*' l4 d$ T- g! b9 S- {/ m+ |0 z1 _
*MISC*# G! o, }) L" R, }! s# p# t
*MISC*7 g0 Q! R/ j: ~% x3 {
*MISC*
8 r( x6 f: P6 E4 Q) a1 @" [ *MISC*- l. [; P# |3 y' K t+ u* s
*MISC*3 a% u9 e) S! {0 r N H* M
*REUSE*% Z3 |2 G4 @7 T9 n2 F; c2 _
*TEXT*
8 [) j+ r8 _2 v7 b+ \9 s *LINES*
0 V2 O) A# X0 x6 c& m1 J, \( { *VIA*; ?- Q! {$ B* ^
*PARTDECAL*
# Y8 i+ ~- M p# @4 E *PARTTYPE*
! ~4 V& _6 S3 S, s$ n* W2 M *PART*' t" p$ N% Z! X( o9 G* ^6 T( u
*ROUTE*
* x. S' E; {+ } Writing routes.3 C s, g- g3 Q6 r5 l2 ^
*END*
6 w7 p) i4 f6 m3 e) A
6 X4 ]6 ~* S1 G) h3 r7 f===============================================================================
: i; L! \( E$ K, t4 h% E PADS layer usage summary:
5 A$ U$ A, D" q2 J Layers 1 to 4 are route layers.
1 g6 v8 ~" E7 u! s- w, f5 N LINES:
4 O$ J" C( e, _4 S' x' X 0 BOARD GEOMETRY - ALL' N. D1 B8 f! L* ^: h/ d: `$ y
1 ETCH - TOP
! z0 L& D0 K, H9 ], P- ] 3 ETCH - INTERNAL2
* q' V/ p8 j, ]- ~ 4 ETCH - BOTTOM6 S2 b4 t) F8 b2 N
9 * Not mapped!/ ?7 m. J& K0 W
10 * Not mapped!
" E' S' H3 W2 J1 C( L1 W2 o COPPER:/ d3 G( ^3 q0 ?0 n. h
TEXT:( P" ]3 G4 U1 Z& ]# B/ J
1 ETCH - TOP$ t8 x g# Q' ?! A: d
26 * Not mapped!
& g n- b- A5 [! V: o9 I* } DECALS:! n+ k% o R; ?" T L8 X( t
0 PACKAGE GEOMETRY - SILKSCREEN_TOP5 `# u+ P! O6 o& |
1 PACKAGE GEOMETRY - SILKSCREEN_TOP
/ N5 e5 h2 M9 V' o# r: q 12 * Not mapped!
. }+ M4 a1 I2 S7 _1 H$ b# G2 L; A 19 * Not mapped!
/ Q' }% q/ F. f Q* ?0 ^ 26 * Not mapped!
' W9 b" P$ k: L' i1 X PADS:/ ]( v& L( z: p- S. F. P8 D5 r
0 ETCH - internal_pad_def
3 r- j% R- m: o$ o7 S! Q+ }8 g 1 ETCH - TOP
, y8 F$ [0 }% {& F2 }2 S% C 2 ETCH - INTERNAL1
8 k( a2 m) I& E& H/ [* M6 x& Q 3 ETCH - INTERNAL2
; @8 k. Q: Y* h4 V# L1 m0 O' ?* I 4 ETCH - BOTTOM0 ?7 P) d. s, f3 \1 C [
6 * Not mapped!! p u( @* z6 N5 ^3 J2 p
15 * Not mapped!
3 h. A7 k. p- P8 ~$ ? 16 * Not mapped!
% l: T" T1 b! K/ c 23 * Not mapped!4 P0 E3 R# [7 D1 T O
VIAS:
5 K: a! U: m l 0 VIA CLASS - internal_pad_def# x& `3 W8 o* H
1 VIA CLASS - TOP
% B4 x2 B1 r+ U! V# V. z1 f 2 VIA CLASS - INTERNAL1. m+ D1 L, j! S( I6 J- }/ w; V
3 VIA CLASS - INTERNAL20 l0 \3 J/ ^0 ^( q9 M6 E1 G
4 VIA CLASS - BOTTOM1 U$ \# I4 a' [, S! R8 \8 F
0 _% U6 q0 }3 ~; O' Z' E9 }/ [ WARNING: 63 data objects mapped to the UNUSED class were ignored.
% P3 m( k/ e' e& I* W' x===============================================================================
4 e" k) d( M) S" R0 e1 q5 ^2 S! `# w$ ` K" c/ H+ o
Creating E:\WORK\TEST\1.brd.& f1 l6 X& N& Z7 R6 y& r
Loading netlist:/ \* t( u+ q4 G/ x# {
E:\WORK\TEST\1.TXT
; ^6 M- w; Z6 a/ e* QWriting database.% f. z3 X3 d4 w1 `0 M( r1 c
ERROR: Error while writing the Allegro database.
|2 ?" i* g. P9 _7 _Closing database.9 r5 {; J- c' C! {2 K3 w
Translation complete.2 `4 ^: m; t, ^( T) D8 Y# K0 e
Finished with errors!) c' m3 e1 m- d6 P3 b$ e+ D# H; d
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发表于 2011-10-12 00:37
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发表于 2011-10-13 13:23
楼主