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Cadence Design Systems, Inc. netrev 16.0 Fri Apr 29 11:35:19 2011
* W2 i& p a. h# _- T(C) Copyright 2002 Cadence Design Systems, Inc.
$ U7 d: L- z* `7 T+ N9 Y4 d7 O------ Directives ------6 @* I- e$ D! \- s
RIPUP_ETCH FALSE;
& Y$ ^% o4 k! |6 i$ ]RIPUP_SYMBOLS ALWAYS;$ W3 ^, e6 U8 T0 K. U, j, u) I
Missing symbol has error FALSE;
& k! V% ~& [5 SSCHEMATIC_DIRECTORY 'Z:/project/907/A1';& \& ~& m# M2 m- t, A1 O7 t
BOARD_DIRECTORY '';
# I9 J) f2 o7 o7 _. sOLD_BOARD_NAME '907.brd';% s0 N+ r, y! F2 g- S+ e! N
NEW_BOARD_NAME '907.brd';
: ]6 O9 J9 ]) p6 YCmdLine: netrev -$ -i Z:/project/907/A1' -y 1 -z Z:/project/907/A1' /#Taaaaaa02688.tmp
* g* \, ]3 O& ^( _' R0 t: d4 {------ Preparing to read pst files ------- k- D+ c$ A* Z3 D6 i+ O
: I3 Y5 ~0 u& q
#1 ERROR(24) File not found9 _& u; F$ y( _+ t
Packager files not found
, z* z4 Q7 m9 J9 c0 v" z#2 ERROR(102) Run stopped because errors were detected2 {/ i5 ]# c, M) N) X- A
netrev run on Apr 29 11:35:19 20110 f ]& E* C& x! H3 R
COMPILE 'logic'2 _( s( h2 f- _) e6 L$ y
CHECK_PIN_NAMES OFF
6 C+ u& y5 O3 W; Q Z CROSS_REFERENCE OFF u8 E8 ]8 w" v! A9 i- ]( R
FEEDBACK OFF
8 _+ V8 S/ Z$ q INCREMENTAL OFF5 k2 @4 o5 G1 j5 p0 n# ]
INTERFACE_TYPE PHYSICAL0 i& I, ?, B; v/ K+ S
MAX_ERRORS 500
& m1 D1 n8 N* n5 w: k& h4 t* G1 G! P- g MERGE_MINIMUM 5
& k8 G# j" x9 H. L5 L NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
1 C4 t. u1 Z$ @$ Q# \" y, H NET_NAME_LENGTH 24
; A" s6 y( e0 f+ F+ C% @ OVERSIGHTS ON
& l+ n" } V& F8 c) b/ g% d5 d REPLACE_CHECK OFF
. I4 q7 f6 g% X( o* u SINGLE_NODE_NETS ON
6 }4 t" i6 y" F8 }2 F; t SPLIT_MINIMUM 0
9 d8 X Q2 m/ l/ a" V SUPPRESS 20; D4 J b7 k b
WARNINGS ON4 Y" ^. H/ u2 _* r
2 errors detected/ P/ I* ]& k) e: O
No oversight detected
) T* p* M! b; b, `. c8 T, \No warning detected6 \ |7 l7 W* a9 x8 \
cpu time 0:00:293 y) G- X4 c! S3 n# y6 w$ O) i
elapsed time 0:00:00
/ o% U4 I' t- b0 C6 B8 \( k, d3 {/ S! z4 F6 w
你好,上面是我将网表导入allegro时出错,情形和楼主的一样,到现在还没找到原因,希望楼主指点一下,谢谢!& j+ m, _3 p& w9 |0 }0 c
封装是我自己做的,PAD和PSM路径也都设置好了,就是网表无法导入allegro. |
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