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Translating E:\WORK\TEST\1.asc.
- F E' y& ]' ?# u) N3 FReading PADS ASCII file header.
) G( B3 w7 |6 D. e! L1 o3 B Version = PowerPCB5.0
8 a6 \) H6 n6 `: [7 n" q, `$ [9 M Route Layers = 4
! H7 q* L, h2 ?3 ^) B Units = METRIC$ H% I( B2 _% \+ u
Hatch mode = Vertical / Horizontal+ ?' r. O- H. l9 ]4 G5 O5 \
Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.000315* [; {3 J. R! l8 l! |: q+ u" H, a
Initializing new database.
* q' X* h5 Q; }, C# [5 F6 d* p4 k5 p Creating layers.; h' U9 S) ~, n1 R& N
Reading PADS ASCII file body.( w- A; f7 Y) h1 }2 O+ b
*PARTTYPE*, l7 Z0 n! g4 C# W( C7 x
*MISC*
$ j- J5 n$ N( ^2 q *MISC*; b9 h$ r# G, M4 @# z2 } `' x
*MISC*
; ~$ ~, ~: g+ E3 ]! W' N0 o; j. b* { *MISC*0 Y8 T3 D8 }. t @7 g
*MISC*0 _+ x4 A" U& ~( V" d s
*REUSE*0 d O5 [1 \9 L0 t& N: S
*TEXT*( n9 u2 P* P" o! ?" e" E2 T b
*LINES** P7 G0 I7 I- |6 q) [2 j4 T1 b, M
*VIA*
. \5 S+ O. [# S *PARTDECAL*
* v7 a' H$ C) }) o+ \/ O$ _4 B/ v *PARTTYPE*
3 p; M, V( r. P1 z7 ` *PART*
! h: N5 I# n+ O; |( @" ~ *ROUTE*
* b% c$ g9 ~2 a: ] Writing routes.
# G6 A1 w. {' b g) [ *END*
O( J8 L4 p- w) s* y" j
1 {0 i, G7 A! J===============================================================================6 ]- V0 U* d. a0 {8 p8 O
PADS layer usage summary:* n5 W6 }, k# u& Z
Layers 1 to 4 are route layers.
. V8 e! B) W+ g; h/ S# W1 y LINES:
9 s7 f% J2 b6 T5 D, `) ?9 P 0 BOARD GEOMETRY - ALL6 D. @) o3 z& {9 s
1 ETCH - TOP d- X. \( x8 T& g; P: s
3 ETCH - INTERNAL2
$ d2 X3 |' a: V0 W9 k 4 ETCH - BOTTOM
2 t- x: g- o. Y7 V 9 * Not mapped!& l( O2 a# |9 r' \ J+ i
10 * Not mapped!
: a' X. l8 R1 I1 f* k, Q* w. D4 s COPPER: G, [& H9 r& o, o* U v
TEXT:7 ]1 w0 D/ P' B# [" d
1 ETCH - TOP
9 R ?4 u: q, M4 d+ o. f9 ~3 Y 26 * Not mapped!. r) f( z& \+ ~7 ~# P5 k+ T! f1 a
DECALS:
: x" E; i7 S6 I0 y- ~! } 0 PACKAGE GEOMETRY - SILKSCREEN_TOP7 w- B7 c2 L9 v$ {+ p* E! Q- _$ m
1 PACKAGE GEOMETRY - SILKSCREEN_TOP
6 ?" Y4 y" y3 M. U- C 12 * Not mapped!
6 U7 ]. R" D& q4 i 19 * Not mapped! ?3 r0 B3 |0 n+ N2 I
26 * Not mapped!& j9 H" t# @ d
PADS:7 t1 |* C$ s; [* h, o ^1 }
0 ETCH - internal_pad_def
5 K" R. D9 `" V. S$ m 1 ETCH - TOP
; u, G2 }( C0 W0 }: ~. j+ x 2 ETCH - INTERNAL19 z! H7 H7 ^ ]6 [! e1 W) l
3 ETCH - INTERNAL2
% O; w( S# j( a+ E 4 ETCH - BOTTOM
2 F/ O% o8 Q3 A5 `; I( E' x 6 * Not mapped!
) U6 ~6 o, J% I$ S( Z8 z2 ^ 15 * Not mapped!
' W* ?- h& P7 c3 s4 A 16 * Not mapped! a% A" M5 L% Z* I' e
23 * Not mapped!
+ d' r o) `6 l: [ VIAS:% l/ b* S$ \' ~& s) g9 V
0 VIA CLASS - internal_pad_def% G1 h) M- a* r4 z: k- K
1 VIA CLASS - TOP
* Z* N8 N1 R$ [' e 2 VIA CLASS - INTERNAL1
' u; d8 v8 b; K% N 3 VIA CLASS - INTERNAL2
$ `# e& I" Q! {9 X3 T' z+ | @& o 4 VIA CLASS - BOTTOM( P8 \/ A$ h A6 E( I
2 _' v7 S5 Z) i9 K6 G1 n; e WARNING: 63 data objects mapped to the UNUSED class were ignored.
4 |# l( ?& @) u/ ^===============================================================================
7 P- L) l( o* i: A; }( d7 P7 }. E5 s) p p. J6 u9 C
Creating E:\WORK\TEST\1.brd.' H* l4 @% n$ j) q$ e
Loading netlist:/ [4 Q& ^5 {4 b2 o. Q" x* B
E:\WORK\TEST\1.TXT: I% B5 S: Q( Z
Writing database.# y5 A% R+ j- X6 V2 U
ERROR: Error while writing the Allegro database.
' G# J# ^0 E2 O! VClosing database.
( i: z9 I7 _' u9 a1 | KTranslation complete.: X8 P- M' M5 E8 I* ~6 U) O
Finished with errors!3 h& i$ H6 t1 h4 G
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发表于 2011-10-12 00:37
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楼主
发表于 2011-10-13 13:23