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DATE: 07-24-2011 HOTFIX VERSION: 002
) J( C t2 i2 g. M6 f% ?. h===================================================================================================================================
, {* t- c% v4 X, E1 w! CCCRID PRODUCT PRODUCTLEVEL2 TITLE
: z. p) M; K( R; x; B5 y===================================================================================================================================
' t9 a: [ w* ^) D8 X% o527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings' C* F. l* y8 T! h; o* f+ H
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
1 V2 ~, t3 N4 q1 c: U592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
% d3 V% M; o! I" N745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.1 {) s; C" h# j% c# O
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
& |+ i& I* o! I( m774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.& \1 y1 y. S; }7 R6 N
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs3 a% x7 J# m$ X; E
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally". Q0 v8 p; z0 C" E9 y1 L2 i. c0 q
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
8 A6 p& K+ S8 J% }' i- c& N3 n, R821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format5 v2 r1 Q- V. \! D
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
; f! h7 X! I* e842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.; ~5 M$ S3 K+ F- s% U
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group/ ^7 E) f# G8 k$ D* N% G8 v
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser3 @4 \9 g0 h8 d% l
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location". v- U0 ~& {* t H
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets2 @4 q# c- t! w
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
9 | ^. K8 [& r$ ]+ o891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
8 g4 m& f) R* r) w893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
: m# V6 N, Q& Y893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.% T8 k c. r) w( g9 m+ X" d
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
7 J2 K _4 l# Z8 n6 R. \895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs5 f& ~4 ]! V% r% _; O4 ?
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading8 z/ }7 ^3 i3 |& Q; ~
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library& z" a5 g/ y7 s' w+ ~
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.5 a1 g, Z+ n) {( B3 n
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.0 }- V) z, y; p2 l8 }
900501 ALLEGRO_EDITOR PLACEMENT "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
' \1 n2 H: u! F$ r# z* I901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.6 i" b- _- o: g8 Z* m6 I- [
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
* B2 H; g8 A, Y) `902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
: y6 X! _) ~% e. f v. x" f902349 CAPTURE LIBRARY Capture crashes while closing library
+ s: p) R+ g; \5 G" k/ ~: y902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.36 S2 z& e( G1 L S
902841 CAPTURE GENERAL Capture Start page does not show
, C( ~2 v1 ^+ h902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
' u7 }6 o8 k+ r8 a& y* ^% c902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
& b! V0 V; f8 [+ \903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?; m) h C& H' }8 y2 }8 c% K! e
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition, \; `; b, Z0 \5 S8 E, o) Y8 G
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
' |$ Z! S5 v5 j! C904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable* f% O. F0 M& b. l8 v" V
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE+ G" g6 l7 h8 b4 i# W
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.33 _- {* X8 v. b D
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
# |0 e \8 e* A" B& T* u904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.# L6 q0 J, \& I+ f8 N6 N, h" X
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3* \% w e' B f1 Z- s5 W
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM$ _* \8 \# S1 t. Y6 l. W
905314 F2B PACKAGERXL Import physical causes csb corruption
) S- s- z$ n6 V0 n0 l905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
z3 T( ^2 n3 N& R6 a) U; S905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible7 [3 K1 }' I( Z9 W2 P. A- J0 R
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues) ^' @, q# P3 ~" J! J; M. T
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid' d1 T0 `7 @1 A3 P$ f! _
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf., T B- k0 M! y- ^/ r" l ]$ A
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.) A: G' U- K- |" r& e0 U
906182 APD EXPORT_DATA Modify Board Level Component Output format0 i* |2 N: g _% d- A6 G% a
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element) e4 I9 r0 `& D; }, A$ A' T
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
7 B3 U' W( v7 w2 _' f* y+ v906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
" p# ~, i- w& B% q4 w6 T0 y5 s906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run9 J# {7 s2 {# \7 j5 T& {
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging8 a- ]( j+ {. @" B* ^7 B1 ^
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'# G3 T( D! J( a
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
: k5 t g) f2 d: u8 k5 j5 s906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin! f4 Q, C3 S$ u: z. B/ n5 M% Z
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used4 z2 O4 S" g) p
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display) ?5 G, Y% z) W) M5 `+ j( t- `* }% `
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.$ g$ ]0 e! i( e
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
9 J/ m. T' r4 L# Q/ z8 r0 [% a$ q907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
4 I$ G7 D& {9 X. l. U907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly% a7 o& e& C8 t, n- |9 d+ n
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
6 c% {( w- u0 f9 C2 ?. z6 M4 [( a907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
9 Q: l9 m- g. @$ G. S908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
( {& w* n% S1 a; V/ @908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
$ ^) `& X6 A" _; [) J, ^& b' q" H908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
! P7 r, j& N. Y7 M# f( d) K% A. [" s908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component. p2 _3 p* t% I6 b F
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.55 q# Z; Z% B: ^4 b4 U7 G
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
% Y' `7 T6 H: k: }0 R& Q. w# Q908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays, B& ^, b4 X# Z- F5 g4 |& P4 f
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes0 T. G# {& w7 M! x) [9 }" m- ~, a
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
/ d m0 A+ Q( v. I' U+ z# `908849 CAPTURE ANNOTATE Getting crash while annotating the attached design, e$ E) C/ P9 k, C: |
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
* R/ ?& K2 z2 i" F909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN1 h& v' x; D# b( y9 u" p( `: T
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.1 l: t& }* i% ?* u# C. X
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
3 a+ v( ~2 [9 b) W r909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
5 K0 U T9 D, Q7 N8 h909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
& |9 }8 ?8 ~7 G2 p909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
: F. _$ ?9 v3 ~4 Z! J4 K0 B1 ]' D909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
, Q0 D v# k K% x910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
7 j! J T% Z2 ^: k% t9 E( }910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
2 b2 j7 x2 ^ Q3 F910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.1 p8 Y$ q* e: n/ ^+ `0 J
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
3 P* x0 N. R5 k' Z" Q! ]0 @. I7 p910713 F2B DESIGNVARI Variant Editor crashes when you click web link under ?hysical Part Filter?window./ U, D- T/ U( `, d
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
. e: H5 S! |5 v Z911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given1 K9 z) h' H: O' X1 ^- }) m
911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
7 k; h' f, c1 j. y912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
6 i" Z8 i+ O! U/ r912459 F2B BOM BOMHDL crashes before getting to a menu5 X, q6 u" V( z/ R
913359 APD MANUFACTURING Package Report shows incorrect data
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发表于 2011-7-27 15:44
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发表于 2011-7-28 07:44
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