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DATE: 07-24-2011 HOTFIX VERSION: 002( p3 o/ Y$ m' X% D1 B4 F9 ^- a
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, B- e) t, ]3 d1 fCCRID PRODUCT PRODUCTLEVEL2 TITLE; `4 H/ B9 x% h+ e" G8 z
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527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
" u& r- h2 w9 z' z' j583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
`& N: O# Q) n$ e% X592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
9 Z- C2 G6 L; J+ _2 M* z745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
& q* W( X; l `; x" I0 c773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
4 e# `2 F0 P1 Q! D0 r774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.! [8 A9 Z+ _) r* T @ G
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs W" l7 Z+ m( `) u
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".. x C/ Z' B" h
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".+ t: z% L5 h! ~8 z. D/ m! z- V- Q
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
- d( ]1 X/ v8 B; \831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
; t) V, q6 N3 I& T0 v+ c842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
2 J! Q8 K( D. n! z854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
8 v6 R6 E8 v) [6 K0 h& F860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser$ s k7 B. [8 k M v! Y C
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
B# Q% |7 h4 p+ Q( v868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets2 g4 x' D# z! F* X& v1 u" I# h# J
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE! ]8 n/ d" m' B1 ]2 w4 {
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments% f3 e2 `! P$ ^7 I
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
y7 f; H; y9 p- H/ }: L# e893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
7 g$ ?6 B+ a3 S, [9 B* D894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command+ c$ S8 j) o# ~ j- \) ~4 e- ~! Q1 ^
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs$ P! [% o9 J a2 G
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading) S8 d& W2 w" P7 q l
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
: j O, e) E. ]" x4 J+ X2 Q898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.4 }* C9 p) I& m
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
4 k% b& V" j* R' l) o4 \2 O900501 ALLEGRO_EDITOR PLACEMENT "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.51 x5 i1 l4 @- D* u0 Y
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
1 z& L( N6 n: ]( x0 S$ r: I901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
# j0 k% ~7 {% y0 V y, v. h* @902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains& `; P$ f& ~9 l% [3 i) `. O* F
902349 CAPTURE LIBRARY Capture crashes while closing library
; s; I" R3 f- k6 R8 c902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
+ t: @4 F+ U9 w2 d4 l902841 CAPTURE GENERAL Capture Start page does not show
, L4 N6 R2 A! d, |3 Q902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
+ R+ e: X( C2 a! j902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
/ U1 G0 @4 h0 Y903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
0 c7 j: Q. z1 Y" b903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
1 j, g* d$ w5 e6 Q; e& Q903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
+ ~; V$ e) K% b9 M1 P7 ^2 M2 p4 @904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable) F/ \3 M1 p8 N# a5 W3 _
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE( J5 N' x# G( V9 ^* E
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
3 a' `; }3 s- R" E* N. B3 F904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places* w6 x( Z# H/ N+ H4 q
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.3 D% \; n0 \+ a4 H" e
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3) U+ i* X) e/ N9 {5 N
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM. f/ D. [% O5 G0 ]" l S
905314 F2B PACKAGERXL Import physical causes csb corruption) G, S( [) o! ^7 M5 E6 U, Z
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
$ z: [# [9 _# W3 j; S7 Z905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
% `- }1 Y0 g- u% r8 y5 |905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues7 C& [' _! R! i% J9 f9 T$ X
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
) O7 H# `) G' L% G/ }906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.4 R! g7 _7 D6 g
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
( @( q) y9 y$ `3 e906182 APD EXPORT_DATA Modify Board Level Component Output format
0 X! b K7 m3 R9 i906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element2 N/ |4 y+ O. n3 @1 ~1 F) K
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.- _$ P+ h! x* g7 U4 Z
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl., y$ O7 M& R8 [
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run; n; |9 |& s. M) O$ M$ X# w, z( D8 e
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
# G6 W1 w; i0 R. e, U906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'7 O8 d& y' `( Z7 [
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation( o! q. c8 @+ L$ B
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin' B9 @& c/ a% H8 _! }1 u& ~
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
/ e$ v2 r/ i% R& M. j5 b0 Z907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display
# s6 f: n& W+ W* z% t J907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.5 ^6 |4 b! F( A+ z$ W" p9 h
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
# C4 m5 Z# R. w907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
) L9 S( ^. v8 S8 h907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
: g2 g' ?8 {3 k' U) ?7 B907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
" U( M* O8 u0 O6 Y, X907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
+ c, w+ ~) U* Y7 q( A _908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
% f4 r$ S2 S, K. h' s908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
) @5 r* X5 A! e; t908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3. w" }; Q: @2 n7 T, U# r% k0 y
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component6 D% i8 S+ ]5 }$ c/ y7 S5 s
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.53 J L% s5 o# {5 i$ E5 u* i
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place1 Z$ j# H2 l6 k: a3 n" J/ I3 `
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays7 u$ t9 ?/ U0 Q. ?- ~" q! b
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes( H) k! z/ L& E+ {
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b! K1 s- K% E6 H' Y8 O
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design9 G1 S# @' A8 a4 p
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
7 b: f* V D3 c; ?& T* a909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN/ E! X2 I3 n0 x
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.& w6 Z) Q+ l. k9 D$ h( _
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
* I: ^$ D9 g) o909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
0 f4 ]. W2 G: W# ?909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning" Z6 T9 N0 ?* K5 I
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack( M% i m) R. j% w
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031- U+ f# l. s7 g: M1 A
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted." |+ e8 w! e+ _" I
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
9 p% f0 q' A5 e) |& ?; s- @. W" m7 n910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.- ?/ x7 _' j/ ?2 t: v9 [
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.52 v8 h% f. X' K$ _# w# d B
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under ?hysical Part Filter?window. o. X& [+ P$ ]" B' g' c
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent9 s" h+ g6 U V- f/ H
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given5 x0 q( z! t' s: S2 d
911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
5 X( P$ E0 t9 P( o912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default+ r1 w# I8 O2 A7 i, F
912459 F2B BOM BOMHDL crashes before getting to a menu
0 Q5 D) B4 ^0 y& A913359 APD MANUFACTURING Package Report shows incorrect data- _" w" r1 i$ ~' f! s6 i5 }1 i
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发表于 2011-7-27 15:44
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发表于 2011-7-28 07:44
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