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![]() PCB Designer's SI GUIDETable of Content
* C, g- C% u$ O1 E0 S% MBasics of SI___________________________________________________________________5
1 K2 F/ C: ?1 {& m1.1 When Speed is important? _____________________________________________5 \: ^* Z' s/ g) T0 ~' \, Q
1.1.1 Acceptable Voltage and timing values ________________________________5
/ y& F" N# p7 P6 m- C. ^1.2 Signal Integrity ______________________________________________________5
; E1 C u, f' L; O1.2.1 Waveform Voltage Accuracy _______________________________________5 + g) j; n& p+ V) I7 F6 z
1.2.2 Timing_________________________________________________________5 & s; p G1 M# C0 C: n" A
1.3 Speed of currently used logic families ____________________________________5 * O! w5 i' x" X
1.3.1 Transition Electrical Length (TEL) __________________________________6 5 Z/ a! s+ S& i4 l j5 h7 C
1.3.2 Critical length ___________________________________________________6
0 i/ {5 Z& o8 t* y1.3.3 What is Transmission Line? ________________________________________6
3 u9 _$ E% E) s8 H1.3.4 What is moving in a Transmission line?_______________________________6 ( r9 |% }' ~: C' r" T: u( {
1.3.5 Power Plane Definition____________________________________________6
( Y- Z% Y7 ]6 _, R1.3.6 The concept of Ground ____________________________________________7 . f# Y& X9 D/ e# R: @' \; }
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7 * g1 B- @9 ?9 G# Q6 K2 ^5 v& k! m
1.5 RLC Transmission Line Model _________________________________________8 1 t0 N0 Y$ j( \+ Q4 D" F
1.5.1 What is Impedance? ______________________________________________8 ; O( M" n/ H R$ X
1.5.2 A Practical impedance equation for microstrip _________________________8
# x: |& ^' n' B9 e5 P1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10
" r/ p# J1 i7 T" `2.1.1 Summary______________________________________________________10 . U9 h) B/ @5 ?; z
2.2 Examples of dynamic interfacing problems _______________________________10 % m* P! }9 @" W& h$ |9 I' Q
2.3 IC Technology and Signal Integrity _____________________________________12
8 J+ L0 _3 |) [1 E0 Z. a2.4 Speed and distance __________________________________________________14 : ^5 ?! h' W) m9 @$ O1 Q
2.5 Digital signals: Static interfacing _______________________________________15
% I, ~' |+ X4 H2.6 Digital signals: Dynamic interfacing ____________________________________16
* i+ n3 ^ K1 j9 T: @, v2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20 4 U+ d C/ f8 L: _
3.1 Summary__________________________________________________________20
3 Q/ k- f% O& y2 `7 N3.2 Reference model for interconnection analysis _____________________________20
6 G/ L9 c* Y4 P$ ~ L6 i0 y3.3 Receiver model_____________________________________________________21 7 q% r! V+ f4 U# ?4 w/ v' d
3.4 RC interconnection model ____________________________________________23
6 w4 I; T$ M8 K7 a j: X |- _3.5 Parameters of the interconnection ______________________________________25
+ N7 u) |, _: M2 ^3.6 Refined models _____________________________________________________26
" r( Q" k3 w; m& ~3.7 Review question ____________________________________________________28 , ^$ k" r. V: R& c% c
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4 Transmission Line Models _________________________________________________31 # U* ~+ w7 l- ]* R
4.1 Summary__________________________________________________________31
9 X9 |% y g' p9 r, {0 F4.2 Transmission line models _____________________________________________31
: C! m, R3 U. N8 @; s O. M# O4.3 Loss-less transmission lines ___________________________________________32
3 G) ?! X, U, j0 ? r- I4.4 Critical Length _____________________________________________________34 9 _- C2 K4 C6 `: D0 i- i* Q
4.5 Reference transmission line model______________________________________35 3 M+ A' l7 }( c4 d: i
4.6 Line driving _______________________________________________________36 9 E8 w+ j7 `" r4 n
4.7 Propagation and reflected waves _______________________________________37 ; x; K% P7 Y6 E* q, Q
4.8 A sample system____________________________________________________39 * m0 ~( v' L; _: X% c2 e
4.9 Review questions ___________________________________________________42 # t4 G0 v9 ]6 N. C0 Y/ X3 l8 a
PCB Designer’s SI Guide Page 2 Venkata
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7 O5 b7 _+ g% a; W5 Analysis techniques _______________________________________________________45
, ~" \2 O) c, U" W) j5.1 Summary__________________________________________________________45
* {3 l, P& Y, X) q# M3 g5.2 Transmission time and skew___________________________________________45 5 Y$ N4 Q: a1 ^1 w/ |$ {' e
5.3 Effects of termination resistance _______________________________________46 ' i* m2 w8 N4 C1 X2 Q a
5.4 Lattice diagram _____________________________________________________48 / E7 z! G+ M# s- ^1 v5 f
5.5 Examples of Real Lines ______________________________________________49
D5 ~% c# \+ N8 K5.6 Simulation code ____________________________________________________51 3 k6 {! r' ~) u' E; g
5.7 Examples of results__________________________________________________54 $ b7 J' f* a3 n
5.8 Review questions ___________________________________________________55 ( {7 u% J E& w1 d7 [# L" j
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+ q7 n7 ?. p& ~9 y) g: d6 Design guide for interconnection ____________________________________________57
9 G0 i4 r w8 W+ H \# w8 y: z. K. C6.1 Summary__________________________________________________________57 * ~8 ]& @7 n- t, J2 [1 I' ]: {- W
6.2 Incident wave switching ______________________________________________57 / z: h3 u% D# Z2 F1 @
6.3 Effects of capacitive loading __________________________________________58
u, V x' O6 k i+ j6.4 Termination circuits _________________________________________________59
* R5 h @ E2 {% |+ s9 V: p' q6.4.1 Passive termination______________________________________________60
0 T4 ]; W) A/ d& F }: d1 q6.4.2 Low power termination___________________________________________61
$ @# C' L. z3 @4 F6.4.3 Active low power termination circuit. _______________________________61 . E/ r$ r+ {2 w( [3 C2 d
6.5 Driving point-to-point lines ___________________________________________62 , v6 H- h1 F6 ~& u! L
6.6 Driving bused lines __________________________________________________64
/ P) j2 n) N' v$ a$ T! d6.7 Design guidelines ___________________________________________________67
* W. k( t6 F; M5 @' S3 k: o8 a# U6.8 Review questions ___________________________________________________67 | 
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发表于 2008-5-26 11:07
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