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![]() PCB Designer's SI GUIDETable of Content
. Y, k" Z4 T' F( u* a DBasics of SI___________________________________________________________________5
2 H$ i! e7 i! U+ o1.1 When Speed is important? _____________________________________________5 : z- h8 |- Q2 a) ?7 O
1.1.1 Acceptable Voltage and timing values ________________________________5 . X- w6 Q8 A& m$ A* e
1.2 Signal Integrity ______________________________________________________5
+ D0 Q' r" p. v1.2.1 Waveform Voltage Accuracy _______________________________________5
. ~2 a8 O) L C; ^# c* F1.2.2 Timing_________________________________________________________5
5 {8 D7 ?+ s+ s$ ?1.3 Speed of currently used logic families ____________________________________5 # `3 f* g2 Z) \( W" Z$ E
1.3.1 Transition Electrical Length (TEL) __________________________________6
( q" `) y: S8 K- ^( W/ A1.3.2 Critical length ___________________________________________________6 # j: r# X0 u8 U$ C' C; [
1.3.3 What is Transmission Line? ________________________________________6 $ J& o x/ L: Q) q
1.3.4 What is moving in a Transmission line?_______________________________6
) L' B$ Z6 b; z3 S- ?1.3.5 Power Plane Definition____________________________________________6 4 ]. w' f" Z3 ^$ j2 s
1.3.6 The concept of Ground ____________________________________________7
0 `" b2 C- ~, ~1 a" E/ K1.4 STRIPLINE circuit with Electromagnetic field _____________________________7 8 @! ~0 J/ t0 W
1.5 RLC Transmission Line Model _________________________________________8
- q0 M" C2 r) e' h8 J" \1 Z- A, M1.5.1 What is Impedance? ______________________________________________8
( y% M% u2 G% h& n1.5.2 A Practical impedance equation for microstrip _________________________8 % ?. U N& W9 `/ n1 U% g# J; I8 }
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10 , _; K+ E: Z A' c8 q
2.1.1 Summary______________________________________________________10 3 B$ i4 ~0 H* R& p: b9 f
2.2 Examples of dynamic interfacing problems _______________________________10
# N' z p1 r2 B. }: L+ ^* N2.3 IC Technology and Signal Integrity _____________________________________12 & N& G$ Z# s9 K3 ?% o' f' T3 U" s! l
2.4 Speed and distance __________________________________________________14
5 ]( k& N: l- k p2 e5 z9 Q2.5 Digital signals: Static interfacing _______________________________________15 : h+ s& X- v- R3 D# g4 j
2.6 Digital signals: Dynamic interfacing ____________________________________16
/ P) B6 p5 G' s5 ~; ~7 ]2.7 Review questions ___________________________________________________18 & c" w6 R& p: u
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3 Interconnection Models____________________________________________________20 2 ?) {. n4 n" z5 ?: R# |, ^0 b
3.1 Summary__________________________________________________________20
7 l$ A- S% w) R8 V. k( e( n3.2 Reference model for interconnection analysis _____________________________20 % c4 Y ~$ }+ F/ v5 T
3.3 Receiver model_____________________________________________________21
( m1 D8 S9 ^0 f* ^$ U3.4 RC interconnection model ____________________________________________23 7 y" D! A$ X m0 p7 Q) L% Q! {
3.5 Parameters of the interconnection ______________________________________25 7 P: ^6 `7 l1 U. p; r* y
3.6 Refined models _____________________________________________________26
% a$ s( v( _ ?9 n) W2 k3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31 2 ^. u0 b1 W0 R- r
4.1 Summary__________________________________________________________31
+ g6 e! z; s8 X3 K* s4.2 Transmission line models _____________________________________________31 $ O- ~* _ F/ J" F
4.3 Loss-less transmission lines ___________________________________________32 6 @5 \/ q( e. Q/ M) v1 \
4.4 Critical Length _____________________________________________________34
/ H+ o5 c( g' n# L4.5 Reference transmission line model______________________________________35 ! R( b+ i7 @4 m% s) e
4.6 Line driving _______________________________________________________36
% V0 S/ `' c% S4.7 Propagation and reflected waves _______________________________________37 , k. \) E# U% v W: ]8 ?
4.8 A sample system____________________________________________________39
0 Q6 h7 M# N9 w& I$ S; N7 x0 M+ @4.9 Review questions ___________________________________________________42
9 \* ^1 m& D: r$ ~PCB Designer’s SI Guide Page 2 Venkata 2 q3 l) z {1 o$ |+ F& h& N$ u
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5 Analysis techniques _______________________________________________________45
5 D8 L' n2 J! s+ Q& {. x2 g: O5.1 Summary__________________________________________________________45 + J, J" P2 z1 `: K& U. c8 H
5.2 Transmission time and skew___________________________________________45 5 u: K( {$ J4 Q2 Z$ }6 e4 I: T
5.3 Effects of termination resistance _______________________________________46
2 \8 m- D( Y2 M6 [ S: ^# k; l8 T5.4 Lattice diagram _____________________________________________________48 . Y0 C! X0 e. R0 d# J0 }: l, }% U" P" p
5.5 Examples of Real Lines ______________________________________________49 8 l4 v. L7 h* e
5.6 Simulation code ____________________________________________________51 % [- q: j$ W6 h% T: u, v E
5.7 Examples of results__________________________________________________54
6 t0 k; v# P( Q; B8 d3 K7 |2 D0 a5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57 : H- d' J2 A/ }: R9 u
6.1 Summary__________________________________________________________57
8 H0 s! g- G Y3 |8 m+ s! ~6.2 Incident wave switching ______________________________________________57 8 B& x) Y) k& N& W, ~" S6 J, q
6.3 Effects of capacitive loading __________________________________________58 . ? I( V& L& T+ n6 [) Z
6.4 Termination circuits _________________________________________________59
! S* I l/ b7 _# }7 b- @4 r6.4.1 Passive termination______________________________________________60 ! u) {8 J. L4 G8 e, E4 V
6.4.2 Low power termination___________________________________________61
+ {+ S# c* ~ _/ \2 r$ _% r1 _- x* T6.4.3 Active low power termination circuit. _______________________________61
% Q' w# p' |# z% U( y) T4 z8 W6.5 Driving point-to-point lines ___________________________________________62
5 ]- D' w- t# N, w: [& T- \6.6 Driving bused lines __________________________________________________64
' S( v8 X* x, M$ p! P [5 V! Y6.7 Design guidelines ___________________________________________________67
; ]; F# S3 W1 R% e; b# @2 J, E6.8 Review questions ___________________________________________________67 | 
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发表于 2008-5-26 11:07
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