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Cadence 站点 上的消息。。。。! n* v) k' I" n5 u) c' b
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New Allegro 16.5 Technology
. k4 [" N$ M! ?# K2 K5 \On May 23, 2011 Cadence will release the 16.5 version of its Allegro PCB and IC packaging technology, providing customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as: - Higher functional density with a constraint-driven flow for embedded components
- Fewer physical prototype iterations with concurrent team desig
- Faster timing closure with new PCB interconnect design planning technology
- n authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations+ K2 d0 I5 a( i+ v |! }
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发表于 2011-4-30 18:50
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