|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
哪位大神过来看看啊，这Altium真让人受不鸟了。/ `; t+ _. V) x+ N$ V# p
最近自己画个图，用层次原理图进行的设计，其中还使用了 harness，结果一编译就出警告“has multiple names”，也不知道哪里出了问题，改了好多地方，包括工程设置，也都不行，上网上查找的方法也不管用。
7 y0 R6 C5 h: \9 _, ] p% o6 X$ X: Y/ F5 J
7 X: d9 Q4 M! B9 V
Class Document Source Message Time Date No.5 V# r8 ~; h3 B
2 G4 L, L3 C3 R7 E% z# {: c" [
[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 29
6 Y X2 t% L) c) K2 K2 v8 x[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 30
; |( ?$ \0 m+ X[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 31
- N/ M( W2 ?/ h! p& A0 h9 ?. {[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 326 E/ z( k8 I- W Z" z& W# w4 m3 _
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 33
* g' e: K3 K7 b" G* j" |5 _, f[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 34
9 w8 R6 ~( l) L0 e0 { A, p$ s0 M[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 35
* M' j$ V- M# A" z# t[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 365 Y: m; t! S& J" R
[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 37" e( Y {0 `3 x) c7 O9 H
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 38* H; e- v Q* }+ v4 [3 k- k: P
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 39
9 }, P V+ K3 x& R) X[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 40
9 t/ h( i9 V/ L% t9 }6 y[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 41; H. W+ H* c! ~6 E% T) z
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 42
/ e; `/ E) h: R[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 43' ]0 h, J2 ^* |, O+ `4 z
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 44
6 B3 A. I& f4 D( L[Warning] TOP.SchDoc Compiler Nets Element[1]: EN has multiple names (Net Label EN1,Net Label EN1,Net Label EN1 (Inferred),Net Label EN1 (Inferred),Port EN_A1) 17:49:14 2016/3/9 45) b$ _' `: T/ `% D! [/ N
[Warning] TOP.SchDoc Compiler Nets Element[1]: L_IN has multiple names (Net Label L_IN1,Net Label L_IN1,Net Label L_IN1 (Inferred),Port L_IN_A1) 17:49:14 2016/3/9 46' G$ Z8 _5 F+ h) c) `
[Warning] TOP.SchDoc Compiler Nets Element[1]: POWER_OUT has multiple names (Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1 (Inferred),Port POWER_OUT_A1) 17:49:14 2016/3/9 47( p' Y! i k" U* ]' r/ _
[Warning] TOP.SchDoc Compiler Nets Element[1]: R1C has multiple names (Net Label R1C1,Net Label R1C1,Net Label R1C1 (Inferred),Port R1C_A1) 17:49:14 2016/3/9 480 j: H& K; E. ?6 D2 E! ^' T
[Warning] TOP.SchDoc Compiler Nets Element[1]: R2C has multiple names (Net Label R2C1,Net Label R2C1,Net Label R2C1 (Inferred),Port R2C_A1) 17:49:14 2016/3/9 49# S. j. V, _5 X8 ^ V
[Warning] TOP.SchDoc Compiler Nets Element[1]: RFB has multiple names (Net Label RFB1,Net Label RFB1,Net Label RFB1 (Inferred),Port RFB_A1) 17:49:14 2016/3/9 504 B/ S& n3 O$ @: p
[Warning] TOP.SchDoc Compiler Nets Element[1]: SS has multiple names (Net Label SS1,Net Label SS1,Net Label SS1 (Inferred),Net Label SS1 (Inferred),Port SS_A1) 17:49:14 2016/3/9 513 B" ?4 y7 z- n4 R
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 52( R) W6 J7 ~8 Y1 F8 ~( c8 e
[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 53
- L0 z7 w1 l) x# y3 C& o[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 54
: [4 J3 w2 |+ v- F$ f[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 55
# y1 a" q C0 ]0 M2 U% O[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 56
, Q) S( n- O+ j: [# F[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 57& u- `: Q d f: _) d
0 H! P T# k: Z ^/ g0 Y2 |( Z0 k9 g- B
|
|
/1 
发表于 2016-3-9 17:54
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
发表于 2016-3-13 15:47
楼主
晕死，好像是因为HARNESS 必须得成对应用。我刚开始画原理图的时候，只在sheet_adc中使用了一个，与它配对的那个没放，结果就出错了，后来都给匹配了就好了。altium 还是有一些不太好用的地方
。再比如说没有差分总线功能，不能单独修改花焊盘，多通道设计序号不能从0开始等等。希望能越来越完善。
