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哪位大神过来看看啊，这Altium真让人受不鸟了。- {7 o2 m! |; p! o0 [. \0 D7 r
最近自己画个图，用层次原理图进行的设计，其中还使用了 harness，结果一编译就出警告“has multiple names”，也不知道哪里出了问题，改了好多地方，包括工程设置，也都不行，上网上查找的方法也不管用。 D: E0 y- N9 T( n4 p9 H
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Class Document Source Message Time Date No.
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[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 29
' P' O9 V4 h6 ^. E[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 300 Y. q; J) H4 b5 b
[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 31# u' }* r* R5 X- {
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 32
$ ^$ s' q$ n$ j' r" E: }( Z[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 33
! A9 }5 _: X" d8 P* `, I5 f[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 341 s+ Z( v; `1 K7 _+ A8 M- ]$ H7 Z" V
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 35: Y7 \6 n, d2 C. ^5 _; f* D, h' G
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 36
, Y$ W7 n3 J5 @+ T# I. X6 M- _[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 37
1 @) ~4 ~& A2 j! w8 {- E+ W[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 38
& J) }& d. g$ A8 O! B& r( Z[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 39
7 `0 v$ Q8 k1 ]9 b. b[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 40% w* R7 l1 J9 l- ]" w- \; {
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 41
1 ` b9 f; C) [/ }+ z s[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 420 p/ y2 S6 g0 d# S- I \
[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 43! R+ _; Z. Q- j& o+ p: w0 X
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 44
; x8 G: [3 [9 U. [[Warning] TOP.SchDoc Compiler Nets Element[1]: EN has multiple names (Net Label EN1,Net Label EN1,Net Label EN1 (Inferred),Net Label EN1 (Inferred),Port EN_A1) 17:49:14 2016/3/9 45
2 E# E# o* o2 n' B" F/ c[Warning] TOP.SchDoc Compiler Nets Element[1]: L_IN has multiple names (Net Label L_IN1,Net Label L_IN1,Net Label L_IN1 (Inferred),Port L_IN_A1) 17:49:14 2016/3/9 46- D& ^3 g) b6 N% A& N8 x3 x
[Warning] TOP.SchDoc Compiler Nets Element[1]: POWER_OUT has multiple names (Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1 (Inferred),Port POWER_OUT_A1) 17:49:14 2016/3/9 476 S3 y, ~& D8 [! n4 ~
[Warning] TOP.SchDoc Compiler Nets Element[1]: R1C has multiple names (Net Label R1C1,Net Label R1C1,Net Label R1C1 (Inferred),Port R1C_A1) 17:49:14 2016/3/9 48& P+ m' Y$ G1 {: D3 `! l
[Warning] TOP.SchDoc Compiler Nets Element[1]: R2C has multiple names (Net Label R2C1,Net Label R2C1,Net Label R2C1 (Inferred),Port R2C_A1) 17:49:14 2016/3/9 49
( Z" ^- ]3 B' n3 d% S3 {9 Q. u e[Warning] TOP.SchDoc Compiler Nets Element[1]: RFB has multiple names (Net Label RFB1,Net Label RFB1,Net Label RFB1 (Inferred),Port RFB_A1) 17:49:14 2016/3/9 504 l7 {% C8 X4 s0 a2 y0 ~3 e r. L
[Warning] TOP.SchDoc Compiler Nets Element[1]: SS has multiple names (Net Label SS1,Net Label SS1,Net Label SS1 (Inferred),Net Label SS1 (Inferred),Port SS_A1) 17:49:14 2016/3/9 515 w! u* H. d3 w4 V+ z7 g
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 52: g* ~& {' t7 @ F8 d* G
[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 53
/ Y" [$ s, z- R% D9 w: g[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 54
) z% K% \3 w% p8 L4 [[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 55( P! q8 B& G. o+ O
[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 56
9 B! p- y5 [0 t, J[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 57
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发表于 2016-3-9 17:54
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支持！
反对！
发表于 2016-3-13 15:47
楼主
晕死，好像是因为HARNESS 必须得成对应用。我刚开始画原理图的时候，只在sheet_adc中使用了一个，与它配对的那个没放，结果就出错了，后来都给匹配了就好了。altium 还是有一些不太好用的地方
。再比如说没有差分总线功能，不能单独修改花焊盘，多通道设计序号不能从0开始等等。希望能越来越完善。
