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/ o8 ]. Q" b7 H8 E 才看到网友说AD15出来了，然后刷微博就看到了这个。。。
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% |3 o1 d2 k; P, g: l- m- |5 F$ }
7 _: U6 F/ h, l2 l' c$ f
' s2 l) p1 D# d0 mAltiumDesigner15.0.7出来了！
0 \" i: \$ [5 Y w) V$ V/ w( u2 g0 O我唯一的感觉就是，Altium，你更新的太快了啊！有事没事，你就更新，5 K% [- e8 W% Y# m
或者说是，你是在修Bug么？？
0 z8 ]' e4 ~- _* L V9 N貌似AD14就一直是Bug不断，这次AD15估计也一样，不过，
1 q0 e& Y$ w! A8 S* H, Y貌似AD15更新了高速PCB设计和GerberX2的支持。具体更新如下。- q; _3 X. d% J
就一个问题，AD总是在不停的更新，是表示软件不稳定呢，还是？？？
& S2 Q, J: B/ y( ^) o或者说，你会更新到AltiumDesigner15版本么？5 u B2 t7 s" c- p9 l& v. K7 I; Y& c: C
& S4 M+ w) Y3 CRelease Notes for Altium Designer Version 15.0
8 s1 r+ D. ?6 C! z) e, ~* Q" cModified by Nikolay Ponomarenko on 17-Nov-2014
! h% i8 w& Z$ ]% h+ s5 k0 i" `Key feature highlights
; `* B+ b$ D5 f) l0 N' yHigh Speed Design with xSignals
; f% C8 N- f& R8 v4 xSolder Mask Expansion Enhancements3 l+ M# s0 D W
Accurate Route Length Calculation& I# j+ `: u6 N
Polygon Enhancements
( }7 I' M" m8 w" s9 ?' O0 bOLE Object Support in PCB Documents ^; P- {9 T1 J1 a2 j# J
Support for Rectangular Pad Holes% \# F8 o* e' |' @+ Q6 J
Separate 2D & 3D View Orientations: ~0 m7 m: E2 J9 B; _/ x& W6 s
IPC-2581 Support
' \# L/ V$ W" ~6 Z" F7 dGerber X2 Support
& q! Z! ]+ l- Y* UIDX Support. y9 R$ t- f2 z8 ]4 L, ]0 B
Exporting to IDF in Unicode Format- N- u1 X/ Y- m# m
True Variants Enhancements
- J5 s- w' S; p7 oOutput Job Editor Enhancements
( g2 ~, u9 L/ q& G& i6 h9 mUpgraded Duplicate UID Correction/ ^+ }7 J5 R3 H
System and Performance Enhancements
. o$ |/ t! j( k0 g6 w( R; z$ dVault Connection Enhancements
3 h4 y& r3 v3 m+ HAbility to Control Parameter Visibility for Vault Components$ H' }( y) L- E
Parameter List Templates0 n {: m$ U9 J1 y" ^) [: m
Parameter-based Name Templates) a4 U3 ~* h L- E* F' S
Vivado toolchain improvements
# ^, i2 S- f# y4 W' G O( LIntuitive Import and Export
& l( A x ^4 V' x0 kVersion 15.0.73 K. U; @/ e% ]" Y) }+ h
Build: 36915 Date:17 November 2014* C3 W4 R0 h/ D$ |- z
1015 Support for high DPI screens using oversized fonts has been reviewed and improved./ x4 j- Y2 f5 B- l5 v' |
1335 PCB NC drill layer pair reports now correctly report layer spans for blind/buried via holes,5 z% _5 |& x: |# d0 z
when layers are shuffled out of default order.
' i1 O# v+ Q# ^1381 Export to AutoCAD now correctly includes thru-hole pad geometries and holes. A2 n0 H! a# K o- P9 r& f
1382 After certain editing sequences the PCB editor would incorrectly switch to masking the display,3 O7 J- A L2 O. @
this no longer occurs.
6 @! H( G6 q5 w. b. [0 V0 @1408 IDF export now includes an option to export in Unicode format.
2 z# s; ?, Z! q5 {- ^& x0 t# q# s; J1615 Changing PCB layer names could result in layer-related lists populating incorrectly and certain2 B+ ^8 y" f2 l. ^
outputs not generating correctly, this has been fixed.9 D6 C0 a6 l; N& ^, Z. s8 K$ O x
2613 A Vault Content Cart can now target regular folders. d6 I$ H1 n8 a7 @
2816 It is now possible to define a CmpLib Component Naming scheme using a template with8 [8 g Q. I* y7 M6 D8 L3 ?
values from any parameter, for example CMP-[Value]-[PackageReference]-{0001}.* ^# z1 E& A1 W y. W$ }6 x2 b! J. x
2817" x0 E# M2 O5 } N4 ^0 b
The CmpLib editor now supports the addition of new parameters via customizable parameter
; B2 h8 `0 I5 ^. M: Zlist templates. Click the Required Models/Parameters Add button to access the templates
, l( H4 s5 b( u6 M/ f. M(samples are stored in the \Templates folder).
F) ~5 N2 m" V, N& T7 \2855 Duplicate UniqueIDs are detected by the Schematic compiler and detailed in the Messages+ Y& J- P& L f
panel. Existing duplicate UIDs are also automatically resolved during document loading.3 ~$ b0 m; a1 n. @- B. ?2 S* F
2910 Release Notes column is now available when using Vault-based libraries in the Libraries panel.9 n3 p3 ]4 h+ h* i3 ?$ _
3006 The Component Cuts Wire mode now functions correctly when the Always Drag option is, K9 d' k" W* R
enabled.9 }5 e3 ~6 F% i/ I3 n& g
30083 ^' K+ e' A" T: ~0 @: o' a) \
OutputJob Editor enhanced by the addition of: mouse wheel scrolling & scroll bars when not+ e" M" q+ j/ Y4 ~6 @, O3 \
all Jobs/Containers are visible, drag and drop to change Job order, multi-Job Enable/Disable! F+ f$ |* v7 T6 T
right-click commands & shortcuts (select the container first).3 U: `+ x: \: n
3026 Import and Export options are now directly accessible via the Files menu. Save As commands
' _: {9 [+ G$ \6 K# p- t3 h) fare now used exclusively for Altium file formats. (BC:1812, BC:2731 partial); h7 L ]4 M/ ?) M2 b
3033 Gerber X2 is now available as an output format. It supports output generation via the PCB& H! ?5 p, Q: X/ M
editor Fabrication Outputs menu, or via an OutputJob." j6 Q/ y: D0 O) d& B8 v: \" P; v
3035
+ V0 n' \$ F, Q3 O8 g( r; zIPC-2581B is now available as an output format. Install the extension and generate output via
e) M) M* z: a3 G$ {2 Uthe PCB editor Fabrication Outputs menu, or via an OutputJob. Download a free viewer from
6 `# y3 z- v0 Qhttp://www.ipc2581.com/index.php/ipc-2581-files0 L1 r/ j( G7 t: x, E, Z$ P9 ^
3081 The Vaults panel now supports changing the column visibility and order. These changes,
- e9 R4 m- P+ [along with panel-section resize actions are retained between sessions.
6 ?* t0 p# b$ k) L3143 Timeout errors after releasing project documents to a Vault have been fixed.
" Z( l7 r% I* A% X: s, d3188 OutputJobs now support using a slash character in the Output Container Name.- `3 ^( A% U- v' z6 h
3189
7 k* N( W: M1 P3 z( T. {It is now possible to pre-configure the display state of Vault component parameters, via the4 r' j/ H$ `3 D& ]
Vault Folder Properties dialog (Type = altium-component-library) and the Vault Library dialog
4 X5 C& O" y* A8 z4 c* O p(add a Vault as a Library).
4 Q, R3 f" `, B+ h3205 Switching from the logical to the physical tab of a schematic no longer leaves artifacts on the
; `' F; O8 }# M& a0 |% k* Qscreen.2 Y& |: H4 N- C' o
3225 Schematic dragging has been further developed to improve wire/bus bending and reduce the p: T) m9 @2 J. r$ N' |2 @
likelihood of a netlist change.# d( g1 x6 y3 J. k1 k) z r. Q w
3227 Schematic dragging has been further developed to improve object handling and the quality of* w) H( m5 i0 B% ^
the result, and reduce the likelihood of a netlist change.6 E O+ j8 H; Z8 M" k
3232 Polygon vertex deletion using Ctrl+Hover+Click is now working correctly. Hold the left mouse
8 ?* S, X( P/ x8 P: H! N& Xbutton down as you click, until the vertex disappears.' \+ C) l2 s% Q6 e3 U9 Y
3251 Releasing projects to the vault with file-locking being enabled works correctly now4 \3 {+ Z9 L/ V& Q
3272 The schematic library editor panel now supports standard copy and paste shortcuts, Ctrl+C
& y0 W, q8 T G4 cand Ctrl+V.8 |) y8 D$ Y( Z+ X" M6 M
3293 BOM filters no longer mix up the parameters. Note that for an existing BOM the filters must be& P; {1 h8 C" Y( ?) I
cleared, the BOM saved, closed and re-opened, and the filters re-defined.7 N4 n4 x+ a) H+ y% k. F
3338 Multi-net routing no longer creates a clearance violation at corners when the Converge
- x4 H( l8 S/ Dshortcut (C) is pressed.
8 F1 V$ o ?, g3 C3341 When a PDF is generated from a schematic that includes a hyperlink, clicking the hyperlink$ `3 I4 O$ G9 H! q1 t
now opens the target web page correctly.
4 L7 a$ h8 I; z: i" {2 E3357 Teardrop removal speed has been improved.0 R% M+ t, M5 b$ T& U' O- f
3381 Second click to select an individual segment in a schematic wire now works correctly.2 R) m8 C; |) H5 ]! R4 W. s% @
3412 The issue with not being able to close documents having "=" character in their name has
+ L' C% o" [6 Q3 ]6 d% I3 y) Gbeen resolved0 n( p! q1 s: N8 V
3419 When the Interactive Router is in push mode, a via on the pushing net can push other-net
) j: n! A' E* aobjects, including vias.
* b- [* z8 u7 v" y R3423 A specific Verilog HDL project would cause an AV on compile, this no longer occurs.( g0 \+ x( [0 ^$ j; k
3425 Update from Libraries now correctly preserves existing location and orientation of parameter) a7 Z* W0 g6 O L
strings.6 ]0 [- B1 k* y. p7 O
3437 2D and 3D PCB view orientations are now completely separate, each retains the previous
% Y& ]8 Q9 K9 W3 N# ~orientation and zoom when switching between the views.- Q3 q4 M j+ j# H+ }3 t6 D: e
3441
* V& T, H& q+ }8 bPin-pairs have been added to the PCB editor, delivering the ability to define the path and
/ A- c5 t; H' |% |: b% Lconstraints for a signal to travel between a source and destination, through termination
7 q2 _6 S+ D8 f5 e5 k# Hcomponents and y-splits.% g: Y1 o# w: J( z
3442 The import of complex arc shapes from AutoCAD has been improved.& T3 ^9 y" _# I/ ?3 i/ A5 T0 A j
3443 The PCB Editor now supports embedding OLE objects, such as Word or Excel documents, into3 `; L, y+ I6 ^- s# L; ]; z: s* e% S
a PCB document (Place В» Object from File).
( r4 x5 w" {3 w% {: c6 l( ^6 Q3456 Xilinx Vivado toolchain is now correctly detected, and can also be added manually in the FPGA2 R$ j! D# x! c& r+ L/ N9 H9 U# Q
- Place and Route preference settings.
5 r Q7 I- l8 N+ r3457 Split plane editing could occasionally cause an exception, this no longer occurs.
$ c9 U0 ?) R7 E. R. ]. r3459* s% W2 J3 j- w! ~6 G
When a wire is placed perpendicular to multiple schematic pins and then dragged, a wire. O2 T1 U% ]6 w( Z3 |! E
segment is automatically added between every pin and the wire being dragged. This fix
+ t0 H! s7 w( I2 @% o8 V( ~ lrestores previous schematic editing behavior.8 W, Q6 _- C5 [. z
3477 Schematic library editor, the Parameter Manager now supports editing parameters across
; ~& l, @, o- }" w+ omultiple selected components.
, [% f) i- u5 X$ C7 L3 c3492 A warning is displayed when you attempt to complete an invalid blanket (has intersecting5 ~4 P: _! Q0 @
edges) in the schematic editor., n2 D+ M0 {" W. @* ?/ ?" I
3495 PCB component fanout now functions correctly when there is an unpoured polygon under the
1 l* G3 e* d1 A7 ?+ c; H) `; ^& Qcomponent.
& Y9 o; M0 I( W7 C n) U( ]9 |: P3497 Click and drag to move a group of selected objects now be functions correctly.9 E, @, X2 r. [
3498 An exception that occurred during import of specific DxDesigner projects has been resolved.+ n. g$ L- D- {8 b
3514 PCB Step model import has been enhanced with better support for curved shapes.) ~9 _# T; l" Y+ H
3521 Fileless editing of an external SIM model no longer generates an AV.
- ~' ^4 M6 [9 m3528 AVS 1.1 is now supported by Altium Designer 14.3.
: L- ?' c a" a/ C7 R8 C6 Z3529 Component pads placed on a signal layer other than top or bottom could not be edited in
; a t0 X T2 @% Zcertain layer-stack configurations, this no longer occurs.
3 B. ?& `* Q/ K4 u7 C: { @3530 Top and Bottom Solder Mask layers are now included in the PCB Filter panel's Layer list., n8 E8 J! I" U
3546 The IPC Footprint Wizard now previews 2-pin and 3-pin DFN component correctly.7 C* j n/ x# v. f
3551 Schematic auto-junctions now size correctly regardless of the wire width.. `! w* O& @( t+ j' g
3556 Component primitives placed on mechanical layer 17 or higher now have their layer displayed5 S1 x) b- r O' S# s
correctly in the Components mode of the PCB Panel.* @. t4 U# u# P N
3560 It is now possible to connect to an SVN repository with a user name containing the @
! ?: |8 j' w: n! Xcharacter.
3 m3 M$ e0 y) R1 Y4 ~3561 The correct Lifecycle and Naming Schema is now being loaded during CmpLib file-less editing.. l/ e% P4 @2 M! ^9 c, s
3567 Model selection drop-downs in the CmpLib editor now display the Lifecycle state in color.
0 `' j3 v4 F3 r3568 The Vaults panel now shows the Note data from the correct Lifecycle state.. Y O6 `6 a* Y: b9 L9 {
3576 PDF generated by running OutputJob can be opened directly from OutputJob document; v( ?" E( f0 R5 k9 w
3577 Simulation model pin mapping now works correctly in the CmpLib editor.
3 t( w# I4 I! ~ ^3585 Pin swapping was not correctly generating an ECO after performing PCB pin swapping, this+ }" e2 R2 g1 c# D
has been resolved.
3 q' h1 ^4 O. }( P, b, C2 P/ z# P( s3592 The path tracing routines used for creating a polygon from selected primitives have been. Q, h* V' A( v' W& C2 U0 N
improved, to better handle small objects and multiple paths.7 c# h4 g2 X) ^) S
3598 From-To panel now shows length taking via heights into account
2 @: y k+ v" m1 h; L4 O5 v- P3611 The schematic Place Wire command now correctly retains the corner mode used in the& u: ~% g2 _1 d2 ?" a( L. f
previous wire placement.
+ G6 i( t* k/ i4 t# y2 k3626 Vault-defined part choice currencies are now used in Altium Designer supplier dialogues
, H$ ?' [$ o! S& n: M R; W& ^3633 Updating Altium Designer from an NIS no longer requires a current Portal connection.
. j. l) w% f2 W# O4 o: o$ B3634 "Access denied" error when installing an update from NIS has been resolved2 K. X! U/ f" ?+ ~
3640 Support for rectangular-shaped pad holes has been added
5 v8 L. d% X! H$ l' ~" t3664 PCB exception while re-building a net to an arc center point in a specific design no longer
' t6 P' x- k$ h4 q Hoccurs.
' h& y. @' d d* b i3681 Plane connects (thermal reliefs) are now shown correctly when board is flipped
3 _5 y8 I9 j5 H' {$ C3689 Exception no longer occurs when choosing PCB font style in VariantManager (BC:4664)
( m% I j M' R8 f4 v0 {3692 Pads with rotated square holes no longer show copper still being present after running the0 y$ Z" g# B5 k: d
Remove Unused Pad Shape command.7 p$ d4 k& f5 ` _$ p! O
3695 GOST specific documents can now be generated in BOM Report outputs! k* q: y: A/ G& b6 _( Z
3707 "No model link found for component" error no longer occurs while editing old cmplib files
- G% d6 d: u/ e. y3708 Clicking on a supplier part number in the Vaults panel no longer causes an exception.
- f9 Y' n& R. H3 }3721 Occasional exceptions during a print preview no longer occur.6 g: B' V+ K' ~. W7 w, z+ g
3722 Under certain conditions changes made in the Variant Management dialog could cause an* r' R) [6 F2 p- }9 e, z5 [# K6 [
exception, this no longer occurs.7 B( b! n) L- l' b4 v* e, D
3729 The Variant Management dialog now immediately reflects changes to components, such as1 R' [; i* D1 X
clearing or choosing an Alternate Part, improving usability.
8 `: W3 ~" a. g" e) M, A+ a3732 The Edit action is now available when right-clicking in the Search results panel in the
+ ^' y2 \# c( L: rVaultExplorer
( G# n4 c. z% M% M. {3736 Fixed error while releasing Vault revisions with extra long file and path names- ~& T# [5 T, G4 l! K
3737 Changes to Comment and Description are no longer lost during component release from the5 G) E5 q1 T/ @5 e5 f: {) {/ f
CmpLib editor
0 {9 {' k3 g( y( P: c3739 A Length column has been added to the Primitives table in the Nets view of the PCB panel- y+ _ I( w$ x6 A$ @" S( P1 d
3755 Scope section of the Teardrops dialog was modified to distinguish TH and SMD pads6 c* b7 V H, {. u
3757 Duplicate Port UIDs no longer cause Port names to be changed when generating a PDF from+ n( g1 ] n1 F8 [+ c; x& b: }
the schematic.
6 h$ h {+ L0 d) i7 X2 D6 k3 M3774 Under certain conditions, schematic compile masks did not exclude components or net
" F# X1 m9 _! q' \objects underneath them, this has been resolved.' d" D6 U) M9 J
3778 On a schematic with a lot of wiring, placing a wire with the Break Wires at Autojunction option+ H+ K3 r9 @. b/ h% f
enabled was very slow, this has been optimized.
! K1 v9 v6 r$ y ?, G$ o& [3 S1 Y* U. i3779 Improved performance of selection and zooming in Schematic in comparison with 14.3) d2 n d( w, k- q; g; H, [
3785 Under certain conditions it was possible to get the PCB Layer Stack Manager graphical h# v4 E* i! y+ P
representation out of sync with the tabular layer detail region, this has been resolved.. @0 K, n; x% M
3787 The " rint as a single job" option in Output Job File documents now properly combines the
( n M' @& i( Nseparate documents to a single print output
9 E2 @7 o9 I8 L3789
2 x2 V& d V2 o! |! P* R2 ? fPCB re-annotation on a variant design with not-fitted parts could result in the varied parts- H1 Z6 X: u9 B; a3 h& N( o2 ^
becoming out of sync, this no longer occurs. Note: PCB re-annotation on a design that uses& y+ C7 p E8 ~' o" h& e' Y
alternate parts with different footprints is not yet supported.( w7 k( A5 z+ C0 L( }7 A
3792 STEP models from Inventor 2014 are now loaded without errors- g% v( `/ @8 g
3800 Variant PCB drawing options have been updated to make it easier to understand how Not
' r, o0 I4 Z! }! R( s# \/ y- b" CFitted components are displayed.: B4 M v3 T; [
3809 It is now possible to specify different values for solder mask expansions for top and bottom
" o0 b& N# N' `4 }8 X& glayers4 l, N8 k4 G8 s! r i/ N- f
3834 Empty surface constructs are now suppressed in ODB++ fabrication output.9 h& {' P$ A2 x& y) \1 p
3835 The IPC footprint wizard now correctly supports defining PLCC packages with different D and E
8 [( Z q" H" D- Z" Fpin counts, allowing packages with any even number of pins to be created.+ E* E6 ^" |5 T
3836 Dragging multiple schematic wire ends could occasionally result in one wire being shorter
' l7 `0 W3 H' C+ G0 Rthan the rest, this no longer occurs.' O6 b$ F( x0 f8 g/ S0 y! ~
3841 Reset All command added to the Variant Manager, use this to restore all parameters to
- z% k. q# F' x% ]alternate or base component values.
) Q% R% N! I, d( N2 Q0 a3844 The issue resulting in "I/O error 103" error message when some of the project files are
3 c; j0 T- E* _* U- O$ p) [2 X, Eread-only has been resolved% Q2 v# S" K8 g1 V. M, ? E% {; Q
3845 The speed of updating from libraries or a database has been improved for designs that5 p. s: m! r% O) |
include variants using alternate parts.+ U+ ?; j3 n# c8 a2 a
3849 In certain circumstances a component would still be shown as varied after resetting+ y" z2 m. S2 B" J0 i
parameter variations, this has been resolved." k8 j9 d5 Y2 o C o8 o
3857 Polygon management was improved in comparison with 14.3 (restored shelving, modified/ `: k1 u3 h! u7 O
concept)
% a# C: U1 X0 \0 }. y9 V3875 The Vaults panel right-click menus now display correctly when Display scaling is being used.
n0 n; d0 T9 S# ~+ X9 m3876 Elements of the Vaults panel were being compressed when Display scaling is being used, this
: m# j* c6 r; g. X Tno longer occurs.+ I+ F- a9 w( a& Y$ l
3888 Crash reports can now be send from behind a proxy
# d- Y3 S n# O L b3889 Simulation Waveform viewer print preview issue has been fixed.0 T6 l$ |2 Y# ~0 D2 R
3900 Class generation settings are now stored for device sheets (BC:3840); w7 D7 l/ j' s3 A/ h6 u$ s/ }- ~
3903 The time to open the PCB Classes dialog has been substantially reduced, particularly on
4 |2 A; J6 x# G: ^designs with a large number of classes.
9 r1 M5 [9 r {9 e3972 ODB++ output did not generate drill data for drill holes included in a panel, when none of the
* f% D. r! Z+ d) O) {) }embedded boards had drill holes, this has been resolved.
2 ]9 _; w1 S1 P0 m# x. ]3984 Drawing of Schematic Blanket directives has been further optimized to get them to draw
V, t9 w" F8 ^* Dquickly and also correctly display the fill color.
0 C8 q' y; j7 G9 a3 `+ G4005 Variant designs that include alternate parts with different footprints can now be re-annotated
" {; h7 c3 |% P1 v8 E5 w8 `6 k7 Sin the PCB editor.
* b! H' e+ B2 w' T4016 PCB DRC now supports stacked alternate parts in a variant-based design.9 [9 z$ f: @" O) }9 D% T
4049 Signal length column was added to Nets panel (this length is being calculated using more
4 S8 _ s9 ?5 Y5 e+ [/ n3 Pprecise xSignal engine)
4 [" n- b% n. l d; [6 n9 E6 J, l; }2 q4062 All extensions within a group can now be installed in a single action.
1 M2 t5 q; D" q; o) O" {4069 Some PCB dialogs were ignoring the board units and always displaying in mils, this no longer
- }3 x6 H2 A {, noccurs.
% X/ j) F4 w" e R9 c5 b* x4 T4076 Modified Polygon rule support check for shelved polygons
6 L1 ], x/ W% p1 @4083 During import of a P-CAD PCB file the layer types are now correctly detected and assigned for
& ]) k8 l) W; p% j" [7 J& ?all possible layer configurations.- H/ c2 k4 V6 c5 ~
4092 The DRC Violations Display page of the Preferences dialog now displays the complete list of
% v5 S9 [1 [4 V* I, ~Display Style entries when Windows display scaling is being used.
% s" H8 X* }+ S# h0 H0 w0 p4098 An AV could occur while placing a pin in a schematic library and pressing Esc to quit the/ m. M, T. t; v! K5 w ]* T$ i
command, this no longer happens.5 n- ~; ^1 r# q _
4111 With a specific combination of preferences, placing a component from the schematic libraries
# a9 z; \; T' X# c" wpanel could cause Altium Designer to crash, this no longer occurs.# \: G: _2 |: G8 L# K/ {
4121 After configuring components for pin swapping, it is no longer necessary for the designer to
# J6 j4 u5 s+ u8 E1 Xmanually recompile the design to make those swap configurations available.& T. ?% Y: t1 E) H
4133 Changes made in the FPGA Signal Manager are now correctly added to the constraint file.
1 j. \0 ~. C7 Y2 s1 I2 t4135 Silk to Solder Mask design rule now correctly detects both silk to solder mask or silk to copper
- i( _/ B- b+ V {2 A2 crule check configurations.1 S$ G3 _. \ u1 C& [! \ u
4215 When a polygon is shelved, connections created by the polygon are maintained internally so
b2 l$ ~+ E6 {* qthe connection lines will not be displayed., r& d7 f- _/ d. |
4351 NIOS II CPU does not generates with Altera Quartus version 13.0 or later- h, h7 k. o1 }8 l. ~0 ?
Source URL: http://techdocs.altium.com/display/ADOH/Release+Notes+for+Altium+Designer+Version+15.0
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发表于 2014-11-21 18:54
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