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Cadence SPB OrCAD 16 最新的升级补丁，版本号16.50.46，修正内容如下：
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1079538 F2B PACKAGERXL Ability to block all їsingle noded netsї to the board while packaging.
7 @5 H% y/ ~4 d8 y4 _1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.) b8 F5 k8 C. T+ A5 ^! M
1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
3 g/ o: m% ?5 m7 ~1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value8 ]& s* y4 @4 V5 | G* ^9 V+ D
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore4 k. _- q: m! p
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.( w: M* f" }& W+ N _" h6 A
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
9 y* e7 r* `1 y6 U, e1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory( E: t R9 z) [: n5 R
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
( {: u4 d& \. P% w' Z1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.4 p- k( U2 K& Y+ \+ ^5 M4 B
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
; w( h& w& D; c' h+ d$ Z0 a1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6., w6 i5 k2 t2 O; ~9 s
1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide./ w/ N) j' J% {6 z* ]0 U
1160004 SCM UI The RMB->Paste does not insert signal names.
9 ^& c) J$ O& R2 D2 `& z4 E P1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
/ j8 a2 f( O" l5 `3 v" D8 G1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.6 A$ g" X% S( C. ^( ~' L% U0 T
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE* i7 g$ C0 ?" {
1165469 CONCEPT_HDL CORE Import Design loses design library name
# Q- a7 a2 }) ^) o1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
; H+ b$ V4 V5 _8 r" c ^: _1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
& ^. O; r3 T, I" s* {1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
! k" i* h8 F$ E. ]1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
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1 y( W0 w/ x: v8 ^' LCadence SPB OrCAD 16.50.46 Hotfix
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Download uploaded
6 Z9 x/ W s* ?- o' U8 r1 Vhttp://uploaded.net/file/9yjz448a/cpborc165046ho.rar% H, f' K" c6 a( O t* n
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Download 城通网盘' O1 J, m1 x! _6 S
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发表于 2013-8-28 21:42
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