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Translating E:\WORK\TEST\1.asc.
+ E& R1 N9 c7 WReading PADS ASCII file header.
3 u# } K, j* T) N Version = PowerPCB5.0
7 t# a& `) K" ]* H6 F. \ Route Layers = 48 c Z0 ?# }2 J/ U
Units = METRIC* I2 k5 v/ \) Z5 c9 o1 ~
Hatch mode = Vertical / Horizontal. \# x* [+ b2 B
Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.000315) K+ B+ a+ d# V5 S0 Q
Initializing new database.- P4 J( z+ b! ~
Creating layers.
. r2 h7 Q% t% ?0 F! c, \* `1 `Reading PADS ASCII file body.! O/ i$ F7 P/ S/ `% E. g i
*PARTTYPE*
; S7 u$ b/ O+ J& S! t' B- h( | J *MISC*
# N$ {1 U3 r, g6 i& k0 P *MISC*
3 y5 Z* I R1 g) ^ *MISC*
2 l# g$ h7 A1 W& ? *MISC*/ n1 t; Q/ f+ o- p
*MISC*: B F- ?, b$ I$ g* T3 I% N
*REUSE*
3 t, p8 X3 Z/ v: ?1 ?6 w M *TEXT*
i4 B$ C' w0 _2 T *LINES*
/ j% l5 k3 h/ A. M! w: u *VIA*! k: v$ `) a: r' J4 p) J
*PARTDECAL*
5 i5 [$ t% L9 y/ `0 g: h *PARTTYPE*4 j R7 D3 k& M# d6 }3 n
*PART*& @. D9 a7 t8 W( b
*ROUTE*
+ m0 R; g' |; }6 a# O3 K Writing routes.' P" h$ ?, U& a) i; N. [
*END*
( _. S$ J, s" R" Z5 I4 T8 B$ x: q3 ~. c# D s
===============================================================================
, A$ m: Q0 F# |# P PADS layer usage summary:: B% e/ y* H) W0 P6 D; R5 [, P. p
Layers 1 to 4 are route layers.
2 v; c) |6 y) i- C( f LINES:8 A3 r1 Z7 X4 }" M
0 BOARD GEOMETRY - ALL
' ~* B+ w) G- C/ r, I' R3 ^' z' G 1 ETCH - TOP
- j i- B3 B& b1 N 3 ETCH - INTERNAL25 z u5 S+ i% x9 y6 W% a$ F( _" G2 S
4 ETCH - BOTTOM
: R" ~& H7 Q( W4 D p 9 * Not mapped!
+ c% y- n4 i" e' C' l# J 10 * Not mapped!0 C. L# Q5 E- V: V
COPPER:
7 Y% }+ _2 o9 o( z8 G TEXT:) ^" @0 C v/ R0 B2 e2 d5 Q
1 ETCH - TOP. F4 g- L; k; _8 M% H, q4 W
26 * Not mapped!6 ?2 Q$ S: Y! \
DECALS:1 ?+ O) ~( F2 _9 {9 J
0 PACKAGE GEOMETRY - SILKSCREEN_TOP
: K; u0 g4 j6 [: n& f6 { 1 PACKAGE GEOMETRY - SILKSCREEN_TOP
' J" C" j1 g( f }- L 12 * Not mapped!" V1 i; s6 J0 ?! i* j9 A
19 * Not mapped!
- f/ b2 o; |" Q" r: e 26 * Not mapped!
; Q; B+ H/ _1 ~' W6 W; K& }: W5 L+ ~ PADS:
6 E8 g3 V# _9 A; c- s 0 ETCH - internal_pad_def' i; y9 Y E+ T R( U/ w
1 ETCH - TOP
- T6 t$ b7 Q" n0 m8 G, i+ s8 J 2 ETCH - INTERNAL1
, \8 z) B# ]: m 3 ETCH - INTERNAL2; V6 k. e; E/ W5 S1 K2 \! i' M/ T1 V
4 ETCH - BOTTOM
( C% d& ]4 }0 B 6 * Not mapped!
" P( | d8 X3 E6 |- U0 u8 c9 J* Q* W* J 15 * Not mapped! F4 F" p S: @
16 * Not mapped!5 f. u' h2 S' S( h
23 * Not mapped!
- M4 s& j! O% b: q3 N- T VIAS:
/ H6 Q5 K8 w: A0 n) V 0 VIA CLASS - internal_pad_def6 A5 v7 T' j+ l
1 VIA CLASS - TOP2 b. `2 b1 d1 z" e
2 VIA CLASS - INTERNAL1, z3 m0 T0 r: u
3 VIA CLASS - INTERNAL2
0 k T3 k) V# |; C 4 VIA CLASS - BOTTOM
5 b" W; M8 n( ^: ]2 d$ c) u8 l; P# R8 m; A+ D) C
WARNING: 63 data objects mapped to the UNUSED class were ignored.8 Q( v/ o3 A8 C
===============================================================================, I' x" A& y7 v3 `
/ Q. G! U2 [$ ?5 Z& X8 b
Creating E:\WORK\TEST\1.brd.
2 \2 |" P6 ^8 ^0 X: \5 XLoading netlist:" U8 A( A- f6 Y+ i1 d
E:\WORK\TEST\1.TXT
5 J$ p( u2 g9 A7 ?, QWriting database./ j' J' i2 H4 j# c$ a
ERROR: Error while writing the Allegro database.
" B. m8 F2 @, G$ [3 ?- ^Closing database.
; L6 u; Y4 e) n+ i9 H% v9 \Translation complete.
( t1 S3 M) |- X- ^8 q' lFinished with errors!
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