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DATE: 07-24-2011 HOTFIX VERSION: 002
$ a3 E4 W7 G* b! C9 O8 }5 r===================================================================================================================================" i6 l5 t# O8 V8 A* t6 r
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 C5 e+ M- q, R' Y4 B+ p
===================================================================================================================================% l( u Z. Y9 D
527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings" i) X" U. t& g
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
t" K, l& Z7 L' k6 S592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
7 Q- _& i' p7 K1 l- J745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
0 y n8 }. r& }- [773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3." d1 C6 Z+ C, [0 u" ]
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.4 y" }1 @3 N6 v- a+ f
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs$ _* ?/ K/ J& `
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
" n3 j/ o0 N4 L; z, f- X810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".. U! h5 ~7 s+ e3 Q' @
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format/ r1 @0 y7 r4 J: h
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself, \0 H; H! F8 |1 x1 @
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias. W v3 z( m; M/ F" H/ _( V! ~ E: T
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
2 J7 z6 y7 ^# O( I860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser& [4 s: S- X2 b ~* E3 r, g; A5 K
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
& A( C& @/ @& W2 Y" P868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets# e7 G7 M+ B X$ z# z
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE( V2 ]7 L8 E* F' C
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments6 K l5 h; E$ I# b" E$ u0 e
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
7 w9 W' s: R4 Z+ e893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
7 b* W% E. g- B894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command- Y* O2 q1 E; |1 }( D* ^
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs3 {8 I2 n4 v2 e4 m
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
& W+ O7 D$ e3 {4 L* _3 M897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
% q9 w1 j9 f0 ~( w6 e# K2 ~4 t898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
; {5 F' D( q# g) o4 ^( j899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
1 {- ^( r5 t* \( ~* @2 K8 I900501 ALLEGRO_EDITOR PLACEMENT "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
' B4 N$ ~6 v' ^901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
8 E; D! m/ \% {& K901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page, Z, E6 S1 S2 }9 _
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains9 L/ ]; h4 x5 p6 U( d/ c
902349 CAPTURE LIBRARY Capture crashes while closing library
* \! G* h$ @/ C1 m# j# H2 \902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
2 P& _7 `; H8 b4 P8 s+ o" o902841 CAPTURE GENERAL Capture Start page does not show0 t+ i% k/ B+ X8 V* _2 M
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5! ? D& c: x, R; o6 g# p
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
% u/ {+ d# F/ S( F& T903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?' R+ K& q1 G8 N. h( Q3 [
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition d" Y$ O% J- A$ P# k/ W1 G. P
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor+ m0 N( ^0 g. M! e/ t2 p- ^3 z
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable2 T3 m8 z: Q6 q' f" x+ @
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE! q" G+ Z [- k% r2 Q
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.30 A, w* g! ^& p" f" ?/ u
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
+ v: c0 C) X: q, l0 `' ]: v! o904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.% V& U+ z: _' Y7 t, ~% k
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
0 ~1 G! I% b* N9 p0 h# ]905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM, A; f" V! D$ L
905314 F2B PACKAGERXL Import physical causes csb corruption; \) l& W% K6 Q/ D8 e7 x+ r4 z: T
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process." o1 `" v8 p; F2 y5 V7 `
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
2 ]2 A) ~% o% }2 H905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues* u$ t- Q5 L; P* y7 W; m6 F
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
6 S" T3 k, _ p9 y906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
2 Q( A: W4 p+ l* M2 O906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
; ]8 q4 I" h! {2 b# C x) w906182 APD EXPORT_DATA Modify Board Level Component Output format* ^$ n* u7 ^% t# P8 Q5 d& j+ V
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
1 Q7 l& D' s* f' R x8 M906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
: j) i' Y, X- t906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
p* x: D) N: Y4 {906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
! F( b) Y: }0 z906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
O4 |" o8 s: `$ f906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design' [* H8 a. e& |1 W1 }$ _& {
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation% [! C# u( f# ^8 m. y# `: e$ Q
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin" c2 D- w \2 b. ^
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used' s1 Y1 Y6 b' r
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display, u8 a; b9 v. C9 T" h; U
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.- h: z. A6 Z; c: R, q
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
7 I3 ]5 q) v* a" y! I2 n907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
3 a# j7 g7 m' a- m907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
4 u& a" U2 A# K L! ]3 D9 {5 k907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional# D1 G" ^5 U3 V1 C! {7 P
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
8 G2 {( S$ m; R2 P908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.7 _2 Z h1 r$ k! P j( S
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name. I* w9 D" w# e) B; [4 u& f( g- n
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3& s* `4 j+ u& s2 T0 J
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
* g }1 d% j1 d9 Q+ f& g908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.56 _* A. X3 f; E& \' \2 O) l
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
" R m8 o5 j, G2 Q908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
3 }) o8 l# G$ ]908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
2 l6 ]+ n% w! H3 `) r1 E' a% x. `/ U908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b( q6 `$ Z3 b, W$ e, }& L
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
. M6 B, \# |6 e908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
c4 N8 [; E9 R1 M. ~+ T2 I909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN2 u* ^, J$ r: a& j) V
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
' E7 |4 ]' m* k909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
/ W, p; _5 }+ k6 P) Q909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout' U" d% U" D7 p
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
1 W: @* A: f' ^! ]/ h909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack4 r l8 w" C% G
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.0315 T+ n/ D F% c0 S1 }$ p+ A
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted. x+ r- T4 O5 O/ k6 M) m( Q
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector% J2 n+ ^ K2 y6 ^& k
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.' E' J4 `: u* L& o. A K& }5 a
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
) l+ W8 b; Y: w8 y% A910713 F2B DESIGNVARI Variant Editor crashes when you click web link under ?hysical Part Filter?window.
- R$ k: v. X! l2 {# Y910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent, C" ]6 g8 Z0 V8 J$ A2 N6 i
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
1 q& y+ x, U! N/ x911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
/ A5 G) \- e0 i" l! Y912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
& T" ?" r; p' ^$ ?! ^: t4 c912459 F2B BOM BOMHDL crashes before getting to a menu
2 j* p3 ]) f! }1 t- ]8 x913359 APD MANUFACTURING Package Report shows incorrect data
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发表于 2011-7-27 15:44
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发表于 2011-7-28 07:44
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