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DATE: 07-24-2011 HOTFIX VERSION: 0024 i. P' @$ K+ U, h: B
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6 Y: d! |; `5 [$ u+ SCCRID PRODUCT PRODUCTLEVEL2 TITLE
. S( l* ~! n; x; Y2 u===================================================================================================================================
- k- ~$ B' s4 o9 D527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
, ^ l! n8 B0 T) I583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.. [6 [; s3 U% S7 ~5 _" P' _! o0 J
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
6 X( E y; T1 G5 \745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.5 D Z, e4 G5 o: C C# e; M" ^
773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
9 w( g1 q( ~+ V* j) n4 K774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.9 v: P% H4 d: x8 @! o5 x2 B6 S
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
+ T; B& V8 ?" t9 f$ z809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".! K M4 l N/ C& ]4 [% z" M8 m+ V
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".3 v. z$ G, \9 i8 B4 d
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format" `, C0 {: T- y- K5 w9 w
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself) P' o: m$ D0 E( I
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.) b+ t6 }4 g* P8 [
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
* y# o4 F1 l; Y& x- ~ _3 P7 x4 A860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser. j3 k, P5 S6 |& [
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"$ p- d7 ~* x7 q2 I( o
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
" B' V9 b# a( ], o# ~882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE7 E: f Q' M, ]/ O; q
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments) O7 A/ O+ i: L3 [$ a' U. I8 v
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
0 v7 _+ F3 h; x0 w8 D2 A893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.3 e u1 f7 A8 U
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
8 {" s; z$ D" k+ ?3 D895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
/ O6 R9 a. P) v( S. B" O896598 ALLEGRO_EDITOR PLACEMENT error message is misleading ^, s. ~7 i7 @$ N/ b
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library2 I7 f( R' Z- d7 M( N
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
; }% e8 W: t: b2 Z: t% }899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
% p# B1 J6 l2 W4 F; Q9 t900501 ALLEGRO_EDITOR PLACEMENT "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.58 p# [! `# Z8 c$ F1 ]& j
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
}4 s( g" s* Q) e901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
' M& Y* x% t4 j1 t3 y902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
4 f' B& O# f8 l6 n0 z! m902349 CAPTURE LIBRARY Capture crashes while closing library3 d0 g. I( i; H0 {0 ]% x
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
1 h- u* m9 w; O C) Y902841 CAPTURE GENERAL Capture Start page does not show
1 |* `2 |+ b8 M O902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
! G8 V, T' {7 O2 ?( m% ?+ \902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
. D/ o8 r: Z2 s4 |903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
* g% i0 {1 [1 u$ Z903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
! A6 Z. M' V/ u1 h# }9 M903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
$ n# b1 p6 }- Y" Z5 j3 S904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
0 k$ T) i% S2 N904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE4 o7 C8 M: e! z6 D
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3% g3 q9 E$ D# v
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places9 H F2 E& ^7 B& y8 s/ Q5 W$ P! c
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.; C4 m/ E3 C4 q& a8 [1 Q5 g: b6 _
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
, Y5 m: a9 D/ f9 m; m; K/ K, @905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM* d9 ~2 d( E1 U! o
905314 F2B PACKAGERXL Import physical causes csb corruption. W c7 |% m2 D' i! m/ X
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
; J; T4 U* G' q( ?( \905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
& y: {/ j9 k9 Z" F! a2 a905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues% t( v$ z5 |- H. S" T
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
8 m+ z6 C1 L+ V5 _$ r& ^906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.0 T6 Q3 [3 b, q* R, s- u9 V/ I; p
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
F- l5 o7 ^+ ]+ e* F906182 APD EXPORT_DATA Modify Board Level Component Output format
6 M! I% r% Z P! ?! Z906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element, Y! \, Q! X; J3 v( W3 o, W
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.' K; n A7 W! Y2 R ~6 Q" x& X
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
/ z7 b/ z- J, c c5 X; @906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
! i! `" z: F, c906673 F2B PACKAGERXL Ignore the signal model validity check during packaging0 w+ x% Z- `, u! q( _( N' \' S
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'/ F# K* k6 l5 @
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation% k4 a! n7 y0 F, k1 s/ N9 q- b' K5 e
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin2 g# ]) E' L9 F' G' |8 N
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used6 D( h8 f8 y) A+ h% f
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display
. {7 `* R$ H, ?8 i m907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.! L+ K7 P/ k# {" M4 b
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"1 B+ v/ L4 L4 L5 J* G" t/ Y9 q' A
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
( l" _$ r) N& d. D907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
5 T/ J5 `# ^( Z2 u- @, a907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional/ I( N" Y; Y# ]5 b6 t" f; d; Y
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
4 J6 m. \$ l ~908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
& m; Q- s! ~0 I. g6 \6 E- h908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
: w: {7 d! } q/ n$ u/ [908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.38 b- T E# D; D& ~5 n
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component" A2 K# N8 }7 h* _, |& T Q
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
8 F' \! T' v3 A7 V3 n% {908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place' M' o7 f/ I7 {) n$ P( T
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays: Q7 H" C! Z2 W1 K
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
7 k; }" l# g# P' ~908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
% @; _1 o l7 ^ c908849 CAPTURE ANNOTATE Getting crash while annotating the attached design) u* D, I4 \6 }; P' O. I
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
: G' V) g9 T: k3 K" k2 M" [( L909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN$ r# T' f( }# m
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
8 J& o) y8 x! A. r909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux1 \7 b% y# d8 p/ ]" w# ~5 k( U
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
3 D+ \; u. c! k, ^ e. m6 W909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
6 k! o" i3 h3 s5 k1 m8 E0 u' B6 m0 H909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack6 G: p) ~0 |7 ^% V+ [
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
: S: W W( z3 }# m# b- P. C910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.; T! y* M& r$ \; `/ P1 R8 ~
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
' Z. A; r4 {8 w: k910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.1 \. W* m3 S# R; n. S6 F2 n7 Q
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
1 P7 C! U( N& h9 f910713 F2B DESIGNVARI Variant Editor crashes when you click web link under ?hysical Part Filter?window.' t% x# k4 j+ W; i) O
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent3 p) A1 X" ]& g6 r% g
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
+ U2 C! A" q! J, W- e- {& T911631 CONCEPT_HDL CORE DEHDL crashes when opening a design5 p& f- c7 c8 ^) |, `9 h. `" @% c3 t
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
$ \- r1 _/ b6 k, Z" a' N912459 F2B BOM BOMHDL crashes before getting to a menu
- b* N$ w/ ~* P: K. S' u913359 APD MANUFACTURING Package Report shows incorrect data6 i$ P* N' k$ b& Q7 w$ r0 \% W6 V& n, m5 Q* N
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发表于 2011-7-27 15:44
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发表于 2011-7-28 07:44
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