|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
HOTFIX VERSION: 002
- U) Y( J, l+ W8 Y, J) f% i) c; r========================================================================================================8 \8 }4 w- \, A" |# q
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; R& w4 z5 F9 ?( H$ p========================================================================================================
* N: c) t% B9 c% d3 E' r1 p511865 SPECCTRA REGIONS Diff pairs should adhere to constraint area1 f1 }2 Z5 k% p6 a: @
564589 ALLEGRO_EDITOR OTHER The show measure command should show the actually measured po4 x( Q& d1 Z( H$ r) R
570861 CONCEPT_HDL CORE Unconnected mark does not be removed even after wire is conne' E- p4 t$ J! \2 d3 K. G; N+ w
572188 APD PAKSI_E 3-D model extract failed
/ w6 r( V( R2 v& t: S578164 CONCEPT_HDL SKILL Cnskill crash during Create Test Schematic step when large pi; O5 U* }& J- h, f$ t
578874 SIP_LAYOUT DIE_STACK_EDITOR Stackup editor in SiP fails to add layers above and below top& S1 t; ~1 i8 p6 h
580315 APD ETCH_BACK Etchback trace fails with error "W- An etch-back trace cannot$ P6 C9 ^: ^2 o" z* [
582308 ALLEGRO_EDITOR OTHER Create Detail for bondpads rotated at (0,90,180 and 270) angl
+ o h3 l# x+ l) C594370 SIG_INTEGRITY OTHER Wrong description in case update form when changing preferenc3 {# D$ T1 {& l! c2 L/ o" e# [
595755 CONCEPT_HDL CORE Rumtime error happen when do Move Group in conceptHDL/ s+ S5 O1 d; T! h9 R! t
597922 SIG_INTEGRITY TRANSLATOR spc2spc doesn not handle inline RLGC DATAPOINTS
- O8 c" U/ {; W606620 ASSURA DRC Problem with density checks in Assura
. q: J$ y$ _/ P2 O# f- U609866 SCM SCHGEN Schgen replaces CTAP with COMMENT symbol which causes net sho5 B4 g4 x& q. w4 E* N
611678 ALLEGRO_EDITOR GRAPHICS During Place > Manual Pins disapear if component is on bottom0 A5 X1 K0 Y* e+ p0 i( U( T$ q; W
615630 ALLEGRO_EDITOR GRAPHICS Pins are not visible when place manually is used for Bottom s
" Q: @, m* X1 m9 M; m9 b5 G615764 CONSTRAINT_MGR TDD BOM report does not filter parts with BOM_IGNORE
8 e& l/ _/ U& x* \616529 CONCEPT_HDL CORE 15.7 Design Entry HDL fails with Out of Memory message
5 N1 a& B& O& r* T5 c' T( z616928 CONCEPT_HDL CONSTRAINT_MGR Net_physical_type and net_spacing _type constraints not sync'6 a) _: h- e1 u- Z: B1 y
617441 SIG_INTEGRITY FIELD_SOLVERS Reflection simulation fails when using wideband vias" S7 x" E: U3 G' _, @- D5 S
617679 ALLEGRO_EDITOR COLOR The color palette will not be saved with the design unless co
- w8 n8 [! x) g& s3 i1 D% k617805 CIS PART_MANAGER Capture_crash
6 U$ h4 d+ C* _, I9 a8 G618988 ALLEGRO_EDITOR SCHEM_FTB Long bus names being truncated
# Y7 c# A/ R. [" [2 ]) a619588 APD EDIT_ETCH Poor routing performance. 5 second delay after each mouse cli$ j- S6 D5 y9 k' g4 u
619691 SIG_INTEGRITY FIELD_SOLVERS Problem of EMS2D by using FreqDepFile
% P+ m! O8 n5 ^1 b: K8 w619867 ALLEGRO_EDITOR DFA DFA_BOUND_TOP shape doesn't display DFA Audit conflicts7 O$ z3 @# u- l3 e& M9 m
620359 CONSTRAINT_MGR CONCEPT_HDL ECSet and Netclass definitions lost in the FTB process
6 C" O: k7 F% u' E- r. E# B# g620424 CONCEPT_HDL CONSTRAINT_MGR CM restore from definition of subblock removes ECSets defined9 R# A' Z: R* j
620700 ALLEGRO_EDITOR PAD_EDITOR Shape has bigger void on Y direction for Oblong SMD Pads
8 n- N l- p( E" U1 C620868 SIG_INTEGRITY PAKSI_E Wirebond material conductivity is not used by PakSI, only a d( b! S, M0 ^" V0 E' ]/ ~: |
620895 ALLEGRO_EDITOR DRC_CONSTR About error message of cns_design command.
: F6 l# x1 `" d# E5 ~) q, {620924 CONCEPT_HDL OTHER PDF Publisher 16.1/16.2 can not output some Japanese characte; c" P, V. J& @2 a
621156 SIP_LAYOUT ASSY_RULE_CHECK ADRC Rule for 揟race Minimum Angle to Pad?not showing all th
. g+ Y3 g& |( K \* E: I621163 SIP_LAYOUT ASSY_RULE_CHECK Ambiguity about the how is the 搒tart of the wire" defined in
( h e1 o- ^6 N# w: a621298 CONSTRAINT_MGR UI_FORMS PCB SI crashes when importing a constraint file into Constrai8 ^6 c4 Z6 G/ c4 H& q
621315 ALLEGRO_EDITOR PLACEMENT Getting wrong component when using Place replicate unmatched% }" v! t0 K) r+ [% T/ {9 J% w1 ~2 |" Z
621848 CONSTRAINT_MGR TECHFILE techfile write fails with Failed writing object attributes
3 d- E2 A* L) x ~. C1 g5 ^4 Z$ K7 t621867 ALLEGRO_EDITOR TESTPREP Transcript window randomly locks up when running TestPrep
3 q7 H# ^* t2 W6 [! i* |621901 SIG_INTEGRITY OTHER Incorrect extracted via drill/pad diameters and missing inter
# t2 i9 _* _( d7 x# W622010 ALLEGRO_EDITOR DATABASE Undesired openings in Negative shape0 _& d! f3 G8 f8 l7 c3 G- N
622062 CONSTRAINT_MGR DATABASE Importing dcf file at system level crashing the Allegro PCB e4 {$ G' v7 o4 s Q( c" Q
622156 ALLEGRO_EDITOR SHAPE Thermal/Anti value producing incorrect void sizes
* N+ O) _& [9 n( q l+ |% o622450 SIG_INTEGRITY SIMULATION Field solution failed
% Y6 i, \! T' Z622466 ALLEGRO_EDITOR COLOR layer priority in 16.2! B+ t8 |. m7 R1 D& R
622566 ALLEGRO_EDITOR SCHEM_FTB Replacing the components of same refdes on board after import
. d4 x9 w* S+ r) O7 X622700 APD PLATING_BAR Plating Bar Check is highlighting Nets that appear to be conn
- p" y/ o% [; y% A) c, m' }622862 ALLEGRO_EDITOR ARTWORK Allegro crashes when we enter a value in the field file size
& Q1 O5 M/ y+ V/ Y o622989 SIP_LAYOUT IMPORT_DATA Type of Wirebond die changed after die import0 ?, S9 t% w2 z! ^1 {( ~
623182 SIG_INTEGRITY FIELD_SOLVERS Extract topology crashed
1 E& p1 w; Z2 f# g U623300 SIP_LAYOUT 3D_VIEWER Wrong placement of Solder Mask Bottom in 3D view file
4 @. k* @& Y! Q# @ l5 g623384 ALLEGRO_EDITOR VALOR Valor output showing padstacks on 45 degree angle wrong in 16
! `* B$ @' e& Y, | i0 h6 a; l+ ^623489 ALLEGRO_EDITOR EXTRACT Allegro tools Report etch length by pin pair takes forever to. g& ?# O* ^3 s7 P3 j F
623529 ALLEGRO_EDITOR EDIT_ETCH Manual tandem diff pair routing has been lost in the 16.2 rel
7 S- d n1 D; X623536 F2B PACKAGERXL packager fails with memory allocation error
* K# v7 t$ U) n H( H8 E3 Y/ h623673 CAPTURE OTHER Unable to get capture window size to full-screen in dual disp' e: h" R6 X' u1 F2 u# X
623701 ALLEGRO_EDITOR OTHER 'Analyze' menu missing when opening Allegro PCB Editor L - Pe3 y4 m0 ^5 a( N; h# T+ J" T
623738 CAPTURE PART_EDITOR Create part from spreadsheet is not working correctly
9 L q4 O& u5 [' e623740 ALLEGRO_EDITOR OTHER Can we use variant.lst file as list file in find filter+ @2 o* D0 K" R. E' p; | @
623745 CAPTURE OTHER Capture crashes when the user tries to place markers( u* K4 C; C Y$ M
623813 SIP_LAYOUT WIREBOND Add wirerbond only is not working in this case with a bondfin
0 F8 e; B' y, z1 u5 @) a6 i. K623830 ALLEGRO_EDITOR MANUFACT backdrilling is drilling through component pads on the bottom1 @/ J$ t _; s1 ~
624048 ALLEGRO_EDITOR OTHER Viewlog for Export to 16.01 is not closing from any of the 'C1 p1 B1 r6 m) ^! Q0 ^
624223 ALLEGRO_EDITOR GRAPHICS disable_datatips variable is busted
/ C2 m# s2 E4 N3 B6 N624495 ALLEGRO_EDITOR SHAPE Static shape did not void to drill holes! X* s7 u5 g; [ T6 v# D9 N
624599 SPECCTRA ROUTE PCB Router hangs on route of design; N: W+ n$ ? t: Q
624653 APD BGA_GENERATOR BGA Generator fails at 400um pitch% a* }6 M* S0 N' J& j4 E9 p
624812 CONSTRAINT_MGR ANALYSIS Importing dcf at the system level causes RPD constraints not
7 o+ Z6 b! H1 M0 s' O624888 ALLEGRO_EDITOR DRC_CONSTR Regions and RCI's Cset not working as expected$ A z4 r$ W) f) M
624958 ALLEGRO_EDITOR EDIT_ETCH Slide in region is changing etch to min line width* Z1 J' w9 D- ~% ]0 ?& r
625251 ALLEGRO_EDITOR COLOR 16.2 Linux allegro - new subclass created does not reflect in: S. ]$ S. S' b0 E& F2 I
625273 APD IMPORT_DATA Import a .mcm into SIP in order to edit the die pins. Edit ->% r, T9 Q+ x) l. Y$ Z+ O, T! q
625279 APD DIE_EDITOR die text in fails when the function name is >31 characters wi) n$ g* O. {4 o6 B
625304 SIG_INTEGRITY IRDROP Need a better understanding of absolute current values report- z; q3 G% [" F
625367 ALLEGRO_EDITOR DRC_CONSTR drc_fillet_samenet does not work correctly% i# Z a- J3 i
625551 ALLEGRO_EDITOR SHAPE Dynamic shape is not voiding to route keepout correctly" B+ {5 K& G0 T0 F
625852 ALLEGRO_EDITOR DRC_CONSTR Some buses in CM are disappeared after import CIS 3 .dat netl% I2 b% M0 w* u
625885 CAPTURE DRC Report misleading Tap connections check for DRC reports error$ a" s3 |3 ?& V, N$ g- H. u
625972 CONSTRAINT_MGR TECHFILE techfile import fails with Failed writing object attributes
$ H+ b1 e, {" }" l) z f626630 CAPTURE NETLIST_ALLEGRO Capture 16.20 hangs endlessly but Capture 16.0 prompts result9 T, [; i% P: P4 r- n5 V `
626669 SIP_LAYOUT OTHER 16.2 radial router find filter does not have option for bond
" s, D0 H6 a1 Q. @2 ?4 H# y626671 SCM OTHER Adding signals in ASA is taking too long
/ R y! R+ e2 X/ w$ I2 T& o627228 ALLEGRO_EDITOR MANUFACT Dynamic Fillet is disappered, when use slide command.
9 m* c+ s7 [2 U8 |6 g4 ]& x, C627289 SIP_LAYOUT DIE_GENERATOR Pins connect at the same net name after Die Text In
" a) u2 \6 v& |' V627864 CONCEPT_HDL EDIF300 EDIF c2esch crashes
1 f( g6 l- C* j L. s# B( d628169 ALLEGRO_EDITOR OTHER write command changes design name in constraint manager9 Q4 K2 c% x/ t9 r2 J8 t
628220 SIG_INTEGRITY SIMULATION Reflection simulation failed with filed solver "EMS2D"" L, x5 p8 i4 h7 d( D0 t
628261 APD OTHER no "Tangent Via Line Fattening" in APD products
" a9 a; g" q$ b i2 L4 C; m628922 APD REPORTS Metal Area Report shows 0.00 on one layer6 \) Y/ T' M! Q
HOTFIX VERSION: 001& i- C! ^: ]3 e7 z3 @
========================================================================================================" }" G Z0 r& U. X U+ j+ ~3 Z: X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 g( C" M% k! m4 k7 Q========================================================================================================
) _1 @! ~1 d! e191020 ALLEGRO_EDITOR SHAPE Shape edits results in same net DRC being reported.4 k4 Z. G2 b3 N, `6 ~
230469 ALLEGRO_EDITOR SHAPE Allegro improve performance of Dynamic Shapes4 w) c6 r+ l5 L# x; |
295039 ALLEGRO_EDITOR DFA Allegro DFA to be enhanced to include height
3 g$ C) B# W0 p3 J346863 CIS DESIGN_VARIANT Variant View mode is not working for multi-section parts
4 @9 d) h' e$ U2 F8 @400036 CONCEPT_HDL HPF nihongo_vector_font should be listed in the Plot Setup GUI- y6 y/ R' S c3 N2 N1 B5 \
410092 CONCEPT_HDL OTHER The Imported sheets loses the write permission for the group; |1 ]8 Z+ ^0 ?: b. |& q) ^6 x
415462 CONCEPT_HDL MARKERS The SPB157 Markers does not normally display the Japanese fon
4 g, r; N2 ]" a4 s6 D, \+ w4 i501802 ALLEGRO_EDITOR GRAPHICS When hilighting parts or nets the system is inconsistent on z4 ^1 s- I7 ?; M& G
503526 SPIF OTHER SPIF is NOT defining class for class to class rules.
, O9 _6 m( Z: e4 }: }2 A511175 CONCEPT_HDL CORE Copy All causes - No object selected error
) s. v# S# M/ V526774 LIBRARY DEVELOPER Pin抯 text size goes back to default size after change pin na" @* D; {- K' l$ ~9 k
533536 CONCEPT_HDL OTHER The font used in published PDF is not identical.
- }! m' N% l0 `/ a537769 CONCEPT_HDL CORE Sporadic behavior of DE HDL toolbars for adding components ge
. w' x8 P) o# y0 W1 W& c, z$ C- J544519 ALLEGRO_EDITOR MENTOR mbs2lib Generating extra "b" version of footprint during tran
4 X8 V$ b: [# i* w8 R551528 LAYOUT OTHER Layout2Allegro L2A translator not translating reference desig
% s) \ ~6 Z; D+ h551614 SIG_INTEGRITY IRDROP Import and export of IR-Drop setup! i- k: K% `; V$ s; D1 S/ N7 Z
552127 LIBRARY LIBUTIL When -lib is missing from con2con PTF files get re-written in+ E9 |1 f/ L' u, Z
560417 ALLEGRO_EDITOR OTHER Part Logic does not read part row from ptf file and assign in
{' T6 ^8 ? N- r2 X; |3 u5 k1 j" e564954 CONCEPT_HDL CREFER Crefer attaches $XR property to other $XR on RHEL.
! }1 `+ \" }0 C2 W+ }& T565798 CIS DESIGN_VARIANT all the sections of mult part package are not coming as DNS i
1 A& w# M: _5 V6 u) ]571627 CONCEPT_HDL CONSTRAINT_MGR cmuprev fails to synchronize constraints on low assertion vec _9 p& }/ S7 N0 ]6 u+ q$ I
577915 CONCEPT_HDL ARCHIVER zero folder is not archived how the archiver is working ? J' l- U) e0 }: F Q) p1 q
581446 LAYOUT TRANSLATION L2A fails with pin numbers do not match between symbols from2 n( Z, T+ {2 D5 |- A
583891 ALLEGRO_EDITOR MENTOR Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)3 I9 C; D$ _( ^6 |9 P: K) Z Y* `! n
586998 ALLEGRO_EDITOR PLOTTING Board shifts towards top left when plotting at higher resolut
% k& M a8 t) X% z0 T& k( d: V: Z5 j587870 ALLEGRO_EDITOR PCAD_IN Import PCAD fails due to dupliate pad name. Caused by a peri
; W$ J3 }4 q' Y: [2 `2 ?3 e588949 CONCEPT_HDL CORE Importing schematic pages from another project crashes Concep) H4 F( B: `. Z
592340 ALLEGRO_EDITOR MENTOR MBS2LIB not creating the correct shape in symbol6 I! {6 n. X1 {, Q
596530 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translator removing/renaming reference design% }$ Q5 s6 Y# W5 o/ {# i
596638 ALLEGRO_EDITOR EDIT_ETCH The timing meter indicates untruthful violation
' }, y% |# B' O6 N% n8 e; l596716 PSPICE DEHDL Flag error due to part pin mismatch while create netlist m) W; Z4 M$ W
597685 ALLEGRO_EDITOR SCHEM_FTB ratnest are out of date error in DBDoctor after import logic+ E: X5 [/ m8 u& F) x; u6 t
597937 ALLEGRO_EDITOR PADS_IN Request PADs_in to translate keepout areas
. K" R( ?5 u" x7 u7 A598575 ALLEGRO_EDITOR OTHER During Split plane should it use settings regarding fill styl5 O: P- @- A, F
598814 APD WIREBOND bondfinger does not move relative to its origin using ipick. z) x4 w9 ~+ { W
599823 CONCEPT_HDL CONSTRAINT_MGR Lost ref to dml-lib causes loss of cm data even if the refere( z( {% i9 d+ p* W, `. K' r8 Y, f
599886 APD EXPORT_DATA bodygen batch tool is failing to generate .css file+ J7 q3 p6 g$ ^0 c2 L2 g
603425 SPECCTRA PARSER Do file fails Syntax error in command unexpected end-of-line
4 j) G# }+ j0 q% h; c( B* n0 E, Z603987 APD OTHER Offset via generator should ensure pitch distance is met or e
+ [8 [4 F$ g$ ?& V9 [# g- k604377 SCM PACKAGER Output board name containing a dash causes scm crash/ p; s" Y. g; C
604614 CONSTRAINT_MGR OTHER netrev is unable to update the Canonical paths with the new d
1 g3 n. V, z2 Q604794 ALLEGRO_EDITOR PAD_EDITOR Replace Padstack reports error pad missing not true.
+ @9 ~1 c7 o% M6 m" @605169 ALLEGRO_EDITOR OTHER Can design_compare handle swappable pins?) n: Y' L' O8 N8 M7 ^2 q/ P! D0 ^
606586 ALLEGRO_EDITOR INTERFACES Multiple drill in padstack cannot be shown in Pro/E IDF
B. C0 J |) t! P, U8 T607217 APD IO_PLANNER wirebond die replacement from IOP
7 v$ J; Q2 {2 r v0 s607222 APD WIREBOND auto wirebonding creates wirebond with DRC
; @! a9 M; s" O5 D7 t607644 ALLEGRO_EDITOR MANUFACT Enhancement to increase the IDF export ''default package heig
/ y4 U. N/ s0 w( o607718 CONCEPT_HDL HDLDIRECT HDL Direct Errors reported while generating simulation netlis
3 G4 w, R, m* H608233 SIG_INTEGRITY FIELD_SOLVERS Convergence errors with analytical vias when drill size is 1
$ N$ l) S% k8 o% T- ^: h) S) ]) W609549 ALLEGRO_EDITOR INTERACTIV Mirror Geometry command to change BB Via's layer.+ H! F& q' Q7 A, ]. C' @; ~
610028 SIP_LAYOUT IMPORT_DATA De assign NC nets during aif import
" ]1 w1 m4 l9 h. g- J, v610134 CONSTRAINT_MGR INTERACTIV Cross-probing from CM to Allegro no longer works on system le+ C! O6 d8 X! D0 D$ A/ C( u9 W
610276 ALLEGRO_EDITOR PADS_IN PADS to Allegro translation is failing with error.
# D1 o5 o3 ^' k& L5 \) v610482 ALLEGRO_EDITOR SCHEM_FTB Netlist swapped net names on 2 pins causing shape to lose its! g# Z% x* s) J" t1 c
610681 CONSTRAINT_MGR DATABASE An exported constraint file can not be re-imported in V16.011 y; W/ Q1 @$ \- w3 E3 V
611260 ALLEGRO_EDITOR DRC_CONSTR Routing a diff pair it does not follow Physical line width se
8 C' x) H6 d2 W7 e( |& w611425 ALLEGRO_EDITOR MENTOR mbs2brd crashes when importing Mentor
" M; u* E L/ A) k611697 SIP_FLOW SIP_LAYOUT octagonal bumps have offset in SIP compared to the chip view
; f4 J* j) C8 H, H0 W8 k7 D611807 APD WIREBOND Duplicate paths created on wirebond import for some cases.
( x8 U! e' i" d# ^611856 CONCEPT_HDL GLOBALCHANGE Ref des deletions after runnning Global Change to change $LOC/ [$ Q( {& V! X: B2 ]/ n6 [7 }
611874 CONCEPT_HDL OTHER Crossprobing one symbol in Concept using Occurence edit mode
0 {8 [. ]' y( X& V; z2 x) d612088 PSPICE DEHDL_NETLISTER Fail to create the netlist for G value expression
- S* i6 i' @2 l; B$ E" l612195 ALLEGRO_EDITOR DATABASE Adding layers to the default cross section causes phantom tex, C% X2 a$ s- W4 l# `0 w
612237 ALLEGRO_EDITOR SKILL axlFormColorize does not change the full background area of a0 O# \- i! S3 z
612299 APD DEGASSING Degassing static shape creates voids inside of voided areas
8 O& V9 a/ w7 i) D9 D( m612560 CONSTRAINT_MGR OTHER Diffpairs don't show the CSet assigned through Net Class f& p" H7 @- ^" m# ]: V
612587 APD WIREBOND Unchecked Allow DRC option creating disconnected wire bond.
3 u7 ~' Y4 E2 g% q$ L: m6 _4 `612884 SIG_INTEGRITY SIMULATION When using ViaModel
+ Z/ f) s: V5 @+ D `" k* E/ x0 V2 s612914 ALLEGRO_EDITOR EDIT_ETCH Centered via option in fanout command not available when swit
" _& r4 c* c9 e1 a- d612939 SIP_LAYOUT ASSY_RULE_CHECK ADRC Continuous Solder Mask check problem
4 H3 }# \- d' W' J5 C613553 CONCEPT_HDL EDIF300 edif schematic writer crash on this design% }/ _2 b% |, E' @: h; ~ y' M R
613565 ALLEGRO_EDITOR EDIT_ETCH Allegro Editor Differential Pairs are routing incorrectly
; E6 O9 Y" r: G; Y5 \613736 SPIF OTHER Spif fails to write class data
; f9 V; Y/ N+ y1 ^$ l. F613990 POWER_INTEGRIT INTERACTIV PI is crashing during capacitor selection9 z* g+ F# [/ V+ m4 Z3 @
614278 CONCEPT_HDL EDIF300 pin text note and flag are not visible on reloaded edif file
- ~& ]! @0 F1 J% l% C0 T; [9 `614371 SIP_LAYOUT WIREBOND Any wirebond command crashes the application
6 k! T( J, {$ ~ E% V614407 POWER_INTEGRIT INTERACTIV PI crashes when editing capacitors' O) M6 l% E, r( ] L( s, X; c
614727 SPECCTRA GUI Allegro PCB Router can not process the dsn and rules file for$ `5 ?, e: r/ a) I2 j8 A8 } ?5 J, {
614972 ALLEGRO_EDITOR SKILL axlCNSSetSpacing does not change the value of the "testvia to7 h# K7 @! t' u
615144 SIP_LAYOUT 3D_VIEWER die placement does not change with changing in soldermask thi# P3 R8 N" d. g! E
615431 LAYOUT TRANSLATORS padstack names are crippled or renamed if it has over 18 Char
/ @' x8 d3 @5 v6 y( Y615506 APD MANUFACTURING Sort by die pin location for Manufacture Doc Bond finger brok
- a# _+ z3 L6 D# Q, u# W0 b. Y; m615745 SIP_LAYOUT DATABASE Move die symbol with stretch etch on is disconnecting wires f
; `4 a: v/ C* c615816 SPIF OTHER Allegro match group members not translating to PCB Router; mi' y) t6 o% D( t! Q
616104 CONSTRAINT_MGR OTHER allegroTechnologyFile XML format issue
f6 I; k- K# O. z7 ~& a7 [' y616122 LAYOUT TRANSLATORS Protel to MAX translator problem with package outlines and re$ ?) z @0 h0 H8 p9 t
616404 ALLEGRO_EDITOR OTHER Design compare fails with message "Invalid input argument" wh" M6 v4 l0 f, `
616713 CIS PLACE_DATABASE_PAR property name with "&" charecter in access database causing c1 I G7 h0 Y6 H
616818 SCM PACKAGER BOMHDL -type scm fails on schematic block8 J6 B& z% }! g/ G( V
616907 SCM VERILOG_IMPORT scm crash during Get Module Name
2 Y* n! Y' P9 N617058 APD WIREBOND wirebond space evenly does not work for fingers on power ring
5 A9 W: f9 ?1 a6 {9 b5 [4 a617083 ALLEGRO_EDITOR INTERACTIV Windows tabs hangs on Linux
& w6 A) _0 b# n% k- A" S617236 ALLEGRO_EDITOR SHAPE Editing a shape in a void causes the bigger shape to drop seg
' }( A0 `* o ~) p( e617351 CIS DBC_CFG_WIZARD XML writer fails if DBC location doesnt have write permission% ?/ j- x1 y& j, ~+ V
617515 SIP_LAYOUT OTHER Be able to invoke Velocity from cdnsip7 G- ~9 ^: a' A# o! l% r
617761 LAYOUT TRANSLATORS Value property for Library symbol of Orcad Layout is not tran1 Z) V M" Z: w! @! j( C- X. J: C
617890 SIP_LAYOUT WIREBOND Push and shove on Bond fingers with multiple bond wires cause6 n- o( s1 a4 @3 a+ `
618184 APD OTHER database diary on unix/linux
" }% d( j9 b+ V2 d3 R r618201 ALLEGRO_EDITOR OTHER Dynamic fillets take a long time to complete
; | Q$ T; K0 s5 k6 W* N' y/ V4 C618545 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we place a package symbol for Jumper usi0 Y7 w' ~2 G* a6 a
618610 ALLEGRO_EDITOR MANUFACT Delete a cline seg creates a fillet
r+ [+ x6 b8 f! c618651 SIP_LAYOUT IO_PLANNER Bondfingers and die are shifted every time an update package
; o# |1 N# Y: M; E j9 x618712 ALLEGRO_EDITOR EDIT_ETCH Shove mode is not working on Diff pairs in PCB Design L7 h8 S6 P5 \4 ^( f! _
618836 ALLEGRO_EDITOR SCRIPTS Allegro does not interpret recorded macro script files proper
4 Q% i: s. e$ n/ O! U, d% N y7 a- ^618946 ALLEGRO_EDITOR INTERACTIV Allegro crashes while using Place Manual -H6 w0 q$ w; F4 M# x2 Q% r: @4 a, @5 r
618984 ALLEGRO_EDITOR COLOR Layers on Allegro Canvas does not match Color Dialog Box
! d- f8 z) l6 a619007 ALLEGRO_EDITOR SKILL Skill command does not accept spaces in file path/name
8 L: {3 F% `5 m$ J. z$ q% z619033 F2B PACKAGERXL Pinswap lost on backannotation
) l! m% c2 l8 H3 I7 I619268 POWER_INTEGRIT SIMULATION IR-Drop can't sees via on pad as open
) [% e1 R) n- c* Z- b9 w619356 CIS FOOTPRINT_VIEW Footprint preview only from 1 directory in Capture.INI4 l9 P+ E. Z- X9 o8 R) t
619712 ALLEGRO_EDITOR EDIT_ETCH Unable to route in the Bubble Mode for Partitioned board. }# z. z: `+ ?; c
619773 ALLEGRO_EDITOR DATABASE Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi2 }! C; M: U* M( m, b
620064 CONCEPT_HDL CONSTRAINT_MGR Loosing Diff pair constraints from lower blocks when packagin! I! e6 V: {/ [: i6 s
622132 CAPTURE NETLIST_ALLEGRO Incorrect ALG0078 error for complex hierarchical design |
|
/1 
发表于 2009-2-11 23:03
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！