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本帖最后由 jacklee_47pn 于 2016-12-21 18:11 编辑 Q X* R5 L& y, m' P! G% O
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來一個強悍的 PSoC® 4100 M-Series
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% S- A$ x' ?, B N4 z32-bit MCU subsystem
7 w% T1 |4 B. O 24-MHz ARM® Cortex®-M0 CPU with a DMA controller and RTC
. n+ n+ w: I3 g3 p9 [6 w8 j! |1 f Up to 128KB Flash and 16KB SRAM- w& {! M' S. u- j/ w: h& `
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CapSense® with SmartSense™ Auto-tuning
( F; ^# E2 C% ^, X! t: V Cypress Capacitive Sigma-Delta™ (CSD) controller
! d+ F* |7 q4 D# ?1 N/ Y9 g8 n2 m CapSense supported on up to 55 pins
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! R; D: Z8 r' T& |# PProgrammable Analog Blocks
. N, w7 F. R% C/ O6 }8 @0 l1 r Two comparators (CMP)
' Z; h: b# g- g/ z2 h Four opamps, programmed as PGAs, CMPs, filters, etc.
& h, P% H* d, @. R5 r7 Z5 k- ] One 12-bit, 1-Msps SAR1 ADC" T j# t) r" l0 a& E7 U5 o1 \6 x
Four IDACs2 (2x 8-bit, 2x 7-bit)$ p: b1 u( Z$ D' F" h3 l9 _" `
! }+ J+ a- }) u. \ qProgrammable Digital Blocks1 F9 U" n1 J( F
Eight programmable 16-bit TCPWM3 blocks
; S* T9 S! N V% p Four SCBs4 : I2C master or slave, SPI master or slave, or UART
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Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),64-pin TQFP (0.5-mm pitch), 68-pin QFN
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