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 才看到网友说AD15出来了，然后刷微博就看到了这个。。。
" {1 X6 O5 a+ q2 E8 E \! ]' H- i7 S, A1 ~
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+ {9 O) p' d4 @6 x: ^9 T' AAltiumDesigner15.0.7出来了！
$ D# G& x2 V$ }6 E: P我唯一的感觉就是，Altium，你更新的太快了啊！有事没事，你就更新，
7 k, C# }2 _: U$ U# ^8 \# h( `或者说是，你是在修Bug么？？1 T% b8 _7 O$ V& ]/ d. |! u
貌似AD14就一直是Bug不断，这次AD15估计也一样，不过，
, s, Y4 s! `: {3 g" {9 P( y$ U, S貌似AD15更新了高速PCB设计和GerberX2的支持。具体更新如下。5 v1 H. N* d/ z+ |& T" n* h7 s
就一个问题，AD总是在不停的更新，是表示软件不稳定呢，还是？？？/ F/ K( m; A3 B; {$ J* l: x$ I
或者说，你会更新到AltiumDesigner15版本么？) \4 J3 n# x3 s9 W9 y% h& i5 c7 {) `- e
) l+ f+ w8 N3 m* b" \' ?) ^9 q4 dRelease Notes for Altium Designer Version 15.00 l5 @, C0 r% h$ V( l* B
Modified by Nikolay Ponomarenko on 17-Nov-2014# f/ G5 q [0 [' u( F, l z% A
Key feature highlights
' F0 O# x# ^% tHigh Speed Design with xSignals& l/ Q, L4 k) l
Solder Mask Expansion Enhancements
( t! J# l) f; }# ?) pAccurate Route Length Calculation
5 X* c; |% D6 G5 O2 nPolygon Enhancements9 _- G! `. B- W- u8 ]8 ~
OLE Object Support in PCB Documents
2 }; j. B' L% r) d1 M) c- WSupport for Rectangular Pad Holes
0 n( y6 S& {. Y* BSeparate 2D & 3D View Orientations
* p2 A5 h' Y" k( fIPC-2581 Support3 t, Q" \& E7 x0 D$ l6 b, A5 H
Gerber X2 Support
. O6 u, w' U2 F) h- G3 {& gIDX Support
1 _! R; e) ]3 {! |' s( wExporting to IDF in Unicode Format8 a+ x5 p( m+ m
True Variants Enhancements
% S' @- q" N2 z, ~Output Job Editor Enhancements$ E. T7 e/ C8 \
Upgraded Duplicate UID Correction* F4 F/ ?1 @% Z, O/ _/ n
System and Performance Enhancements
. l8 F- W% i# A% i/ W, S! }8 P! iVault Connection Enhancements' Z- s& r1 }$ s
Ability to Control Parameter Visibility for Vault Components
+ T% L. z9 P+ S1 m4 i _8 BParameter List Templates
0 C; V! c4 R5 w4 vParameter-based Name Templates2 \7 Z' O: T9 Z6 T2 t% a
Vivado toolchain improvements' S3 w( Y7 O8 Y9 S# ]4 b: W+ n
Intuitive Import and Export
2 ^/ {" l6 ` X) B, i' ]7 v. L! N' U5 dVersion 15.0.78 z1 _; f) @( j4 s
Build: 36915 Date:17 November 2014
* N) {# g7 x9 C$ G* P4 |% S1 f( H1015 Support for high DPI screens using oversized fonts has been reviewed and improved.
/ N; v1 y6 f5 s2 N% X8 g1335 PCB NC drill layer pair reports now correctly report layer spans for blind/buried via holes,2 S8 O- k: B5 X6 L g$ ^- i) h
when layers are shuffled out of default order.! a* v* B, y4 K6 v6 f7 R
1381 Export to AutoCAD now correctly includes thru-hole pad geometries and holes.
# @5 U' g6 v# i7 `/ ^1382 After certain editing sequences the PCB editor would incorrectly switch to masking the display,
9 e( U( j% o) B& Z+ R9 I+ h4 U' Uthis no longer occurs.
9 N1 B+ k* S, V1408 IDF export now includes an option to export in Unicode format.( [/ D5 ]6 J# C/ C/ O# _2 ~
1615 Changing PCB layer names could result in layer-related lists populating incorrectly and certain
$ t) B# @) U4 E1 X boutputs not generating correctly, this has been fixed.
& j6 Q$ [+ P9 X# ^- n7 f9 t2613 A Vault Content Cart can now target regular folders.
9 I0 P2 H: K2 p% o; F( l+ l2 F2816 It is now possible to define a CmpLib Component Naming scheme using a template with
/ m* q) b3 Z% q, _values from any parameter, for example CMP-[Value]-[PackageReference]-{0001}.. i- H( K0 h7 Z( r# E8 p& |+ Q. ^
2817 a* U4 B }/ K
The CmpLib editor now supports the addition of new parameters via customizable parameter" D( x& D7 l: D" Z. x
list templates. Click the Required Models/Parameters Add button to access the templates
, j0 Y- q% F9 Y7 W; d* j(samples are stored in the \Templates folder).
* ~9 `! N& w. H* r& [2855 Duplicate UniqueIDs are detected by the Schematic compiler and detailed in the Messages
' P3 @2 g* c& a3 V* h& @panel. Existing duplicate UIDs are also automatically resolved during document loading.6 v4 j* k9 w" }5 ?1 ]( R C
2910 Release Notes column is now available when using Vault-based libraries in the Libraries panel.6 G1 A+ r; a; n
3006 The Component Cuts Wire mode now functions correctly when the Always Drag option is) E% m9 r: {) T
enabled.
0 U3 [$ Q* Y( V30087 Y# l) X# }' E: Z# C& [) @! j
OutputJob Editor enhanced by the addition of: mouse wheel scrolling & scroll bars when not" J; Z# @6 t. L) z" C
all Jobs/Containers are visible, drag and drop to change Job order, multi-Job Enable/Disable) U1 |4 c3 b$ X j
right-click commands & shortcuts (select the container first).) d! e, {- u4 h# V: x* x
3026 Import and Export options are now directly accessible via the Files menu. Save As commands0 Z: w* \- {7 N2 o
are now used exclusively for Altium file formats. (BC:1812, BC:2731 partial)
$ R5 l# Y! W# N/ L9 c/ e) r; t3033 Gerber X2 is now available as an output format. It supports output generation via the PCB
0 X8 c0 f" H2 Jeditor Fabrication Outputs menu, or via an OutputJob.- o# P c0 e6 T8 r% {; C
30358 S% s: _% Y1 o' g0 x' X
IPC-2581B is now available as an output format. Install the extension and generate output via) {9 s5 A o& v6 i4 K3 w
the PCB editor Fabrication Outputs menu, or via an OutputJob. Download a free viewer from# Y, K/ a X. |# @( M# n
http://www.ipc2581.com/index.php/ipc-2581-files% I1 h# c* t3 J$ }% L0 ` L5 M, k
3081 The Vaults panel now supports changing the column visibility and order. These changes,
, V1 q* A4 {! v; e+ Q% \* `" E$ |# `along with panel-section resize actions are retained between sessions.. p! k, H0 \9 S& w/ i
3143 Timeout errors after releasing project documents to a Vault have been fixed.
/ W. S8 ?& u0 R! e8 J3188 OutputJobs now support using a slash character in the Output Container Name.* T- ?$ p* I# }1 y- h: t8 L" n3 R+ d
31895 Q9 K) d- t' z- Q
It is now possible to pre-configure the display state of Vault component parameters, via the: R7 y& X1 r r7 z p7 }" B
Vault Folder Properties dialog (Type = altium-component-library) and the Vault Library dialog# x% @# J# _3 P/ _% _: z2 b' q
(add a Vault as a Library).0 k9 h }, Q, z! o+ |2 Z, M
3205 Switching from the logical to the physical tab of a schematic no longer leaves artifacts on the
* W5 C4 ?- a) Iscreen.5 |# C; N1 H* G" \& T' P0 k
3225 Schematic dragging has been further developed to improve wire/bus bending and reduce the
% R8 h1 c$ A" J6 m8 e6 tlikelihood of a netlist change.
7 u, a% w6 f& h! n0 \3227 Schematic dragging has been further developed to improve object handling and the quality of" e% K0 U, e9 g) F0 c
the result, and reduce the likelihood of a netlist change.
4 q2 l E3 S7 g$ R: R! H3232 Polygon vertex deletion using Ctrl+Hover+Click is now working correctly. Hold the left mouse; d9 Z: a/ y1 ^3 h) U
button down as you click, until the vertex disappears.; U2 W5 L; W0 u. \8 n( s
3251 Releasing projects to the vault with file-locking being enabled works correctly now! Y6 Y9 C1 n! P) \
3272 The schematic library editor panel now supports standard copy and paste shortcuts, Ctrl+C; r" \$ F0 @5 G- F( k9 Y& V$ o
and Ctrl+V./ q0 y! F" h: S7 t- I
3293 BOM filters no longer mix up the parameters. Note that for an existing BOM the filters must be
/ }! c' N& L# w: | vcleared, the BOM saved, closed and re-opened, and the filters re-defined.
g* f3 G' X- C1 {3338 Multi-net routing no longer creates a clearance violation at corners when the Converge
5 {, G+ u' [% Jshortcut (C) is pressed.' E: J P7 P/ l+ ]- L
3341 When a PDF is generated from a schematic that includes a hyperlink, clicking the hyperlink; I/ K4 J V# A
now opens the target web page correctly.* X1 s9 J' B7 b
3357 Teardrop removal speed has been improved.
( T: ]3 m; H8 { q, `, U3381 Second click to select an individual segment in a schematic wire now works correctly.
1 x' c+ _+ e- t3412 The issue with not being able to close documents having "=" character in their name has
8 ^* u$ e! M/ z. Dbeen resolved
3 M' f6 e* o- R! M+ U3419 When the Interactive Router is in push mode, a via on the pushing net can push other-net
, s7 C: d+ }$ m$ ~objects, including vias.
: @4 w6 _, O8 Z3423 A specific Verilog HDL project would cause an AV on compile, this no longer occurs.: U0 ] B) h* \- I+ `( A b
3425 Update from Libraries now correctly preserves existing location and orientation of parameter
% {' q; X4 P4 Z9 D- Dstrings.3 H0 e4 C! K$ a8 k$ Z+ Y+ _5 {
3437 2D and 3D PCB view orientations are now completely separate, each retains the previous
! E7 ?( q! r! G0 [/ worientation and zoom when switching between the views.& W# O4 y: m5 O4 Z/ m& t
34416 _4 P6 q7 g2 j, _
Pin-pairs have been added to the PCB editor, delivering the ability to define the path and2 k( b6 _2 V$ O8 `9 ?) T
constraints for a signal to travel between a source and destination, through termination
3 x' c" V! C! G6 i2 W/ h) D4 |' L3 l' Wcomponents and y-splits.% X% Q! Y6 H1 x2 b# @
3442 The import of complex arc shapes from AutoCAD has been improved.
5 k8 d8 Y }1 r& v6 o3443 The PCB Editor now supports embedding OLE objects, such as Word or Excel documents, into
0 a" F; m% K+ Q" f( P' a9 F# O% R+ za PCB document (Place В» Object from File).
, P5 M& d) Q8 C0 ?7 _3456 Xilinx Vivado toolchain is now correctly detected, and can also be added manually in the FPGA) B* c+ U2 H' r
- Place and Route preference settings.
# }& j* q; v. M' Z& H1 H3457 Split plane editing could occasionally cause an exception, this no longer occurs.3 U8 s' r% n' i% z9 \6 a0 X# E9 {
34595 s/ j3 U. J7 i$ v4 U3 T
When a wire is placed perpendicular to multiple schematic pins and then dragged, a wire e6 x# ~0 Y1 t, h! C3 m
segment is automatically added between every pin and the wire being dragged. This fix
1 w" I% P* M8 t8 arestores previous schematic editing behavior.
. r1 c8 ]+ `( W: V2 }3477 Schematic library editor, the Parameter Manager now supports editing parameters across$ P# ]3 n, _& g: }
multiple selected components.& \8 p! A0 D/ P. }# C+ H
3492 A warning is displayed when you attempt to complete an invalid blanket (has intersecting% `* @5 u6 j/ Z" @! p/ x" F! m
edges) in the schematic editor.
5 ?* P- D& ` @! s/ M3495 PCB component fanout now functions correctly when there is an unpoured polygon under the
! ^* f' Q2 N" D+ R! L" V' y) Tcomponent.
: a/ `' z7 M+ r% m# s" R5 J3497 Click and drag to move a group of selected objects now be functions correctly.5 _' e6 }/ H5 N* f% x
3498 An exception that occurred during import of specific DxDesigner projects has been resolved.
3 t; L, ?* P* s+ P- F3514 PCB Step model import has been enhanced with better support for curved shapes." e9 S- w# Q) V6 K
3521 Fileless editing of an external SIM model no longer generates an AV.5 z$ {% {) z6 s& M
3528 AVS 1.1 is now supported by Altium Designer 14.3.
# t) R1 n7 \' S* G4 ]3529 Component pads placed on a signal layer other than top or bottom could not be edited in7 m4 f* K* u. @3 }
certain layer-stack configurations, this no longer occurs.
4 T6 q1 f3 o2 D( z3530 Top and Bottom Solder Mask layers are now included in the PCB Filter panel's Layer list.* {- N7 V9 M0 ^
3546 The IPC Footprint Wizard now previews 2-pin and 3-pin DFN component correctly.
- @' a4 l9 S) o7 g+ k3551 Schematic auto-junctions now size correctly regardless of the wire width.
( k# _$ ~4 o+ h# d C- D$ O3556 Component primitives placed on mechanical layer 17 or higher now have their layer displayed
& l" }( {2 g9 s1 K7 A( Ecorrectly in the Components mode of the PCB Panel.; d: h) _/ [1 s
3560 It is now possible to connect to an SVN repository with a user name containing the @8 M: m7 \' F1 F. f. \* F4 |
character.
+ U: M! o( G$ j. X3561 The correct Lifecycle and Naming Schema is now being loaded during CmpLib file-less editing.
0 y$ y4 E, F1 V: z f; l6 v3567 Model selection drop-downs in the CmpLib editor now display the Lifecycle state in color.
+ m! _! A3 X: u3568 The Vaults panel now shows the Note data from the correct Lifecycle state.
& k1 U" u; y0 F7 E3576 PDF generated by running OutputJob can be opened directly from OutputJob document
1 S# B r- W! `/ h4 X0 l- E3577 Simulation model pin mapping now works correctly in the CmpLib editor.
0 F+ `1 Z6 r" ?/ C; b. B! K; X8 }3585 Pin swapping was not correctly generating an ECO after performing PCB pin swapping, this% \& w6 H: X: c% H W% X
has been resolved.5 p, a8 R% s; R+ l* j
3592 The path tracing routines used for creating a polygon from selected primitives have been( C; L, J. \6 h" t! w0 k
improved, to better handle small objects and multiple paths.
. g+ z8 X9 I& I' } u! P3598 From-To panel now shows length taking via heights into account
; ]: }. k6 T l0 K4 \3611 The schematic Place Wire command now correctly retains the corner mode used in the
$ L$ K: D% Q% i4 F! H2 ^4 x2 T/ vprevious wire placement.& M0 K$ U" N6 s" f+ U' V% `
3626 Vault-defined part choice currencies are now used in Altium Designer supplier dialogues( m* W4 d- j s' c5 X
3633 Updating Altium Designer from an NIS no longer requires a current Portal connection.
; _+ L0 _: k/ a# w" q' i3634 "Access denied" error when installing an update from NIS has been resolved: \5 W+ H z9 Q5 e q/ Q) Y- Q
3640 Support for rectangular-shaped pad holes has been added
0 J: U) j9 E( U5 ~6 x4 }! R1 N* U3 s3664 PCB exception while re-building a net to an arc center point in a specific design no longer; T! N, ^5 Y" ^2 _' J, E" ~0 N, O
occurs., v- R2 F5 c" ^
3681 Plane connects (thermal reliefs) are now shown correctly when board is flipped. D% d3 p( p% c! C1 h% p) O
3689 Exception no longer occurs when choosing PCB font style in VariantManager (BC:4664)( C# R8 X* g# \
3692 Pads with rotated square holes no longer show copper still being present after running the6 [' |. K( C; c1 m
Remove Unused Pad Shape command." u+ s) }9 I. p8 H5 c
3695 GOST specific documents can now be generated in BOM Report outputs
# A9 L5 ]+ }9 [% F; N0 j3707 "No model link found for component" error no longer occurs while editing old cmplib files; n2 X- L' {/ g# A- U' g( H
3708 Clicking on a supplier part number in the Vaults panel no longer causes an exception.
: D4 G0 L3 Y- \0 `; a1 j3721 Occasional exceptions during a print preview no longer occur.
" j7 }9 [, h8 g5 K C C. r3722 Under certain conditions changes made in the Variant Management dialog could cause an
) b, r+ Q& H! Kexception, this no longer occurs.
% X2 O, B0 o6 p1 y. A3729 The Variant Management dialog now immediately reflects changes to components, such as
# Y8 e) F- W0 {, p0 _clearing or choosing an Alternate Part, improving usability.: n+ g9 `+ _8 a5 i% ?% U- b( u8 c
3732 The Edit action is now available when right-clicking in the Search results panel in the
! L6 k* ~7 P- ~1 p' tVaultExplorer2 _2 D, L$ i- ~+ n: F. W# y" I. E
3736 Fixed error while releasing Vault revisions with extra long file and path names
H% h9 g3 A x! i8 i* z3737 Changes to Comment and Description are no longer lost during component release from the
4 E: Z* F" ~& hCmpLib editor
) l6 m( G. g" P1 ]! ]0 f3739 A Length column has been added to the Primitives table in the Nets view of the PCB panel$ G5 @) ]+ l" {; z" i
3755 Scope section of the Teardrops dialog was modified to distinguish TH and SMD pads
" Z& U3 f- w& H" |) \: n3757 Duplicate Port UIDs no longer cause Port names to be changed when generating a PDF from
/ s: t! w% m9 r7 B4 [the schematic.9 u, ]0 u0 G4 x/ p, U$ F
3774 Under certain conditions, schematic compile masks did not exclude components or net9 p6 z n9 Y0 J' \( m
objects underneath them, this has been resolved.% H# c; D# q, W; I* K$ |; ?- P8 }
3778 On a schematic with a lot of wiring, placing a wire with the Break Wires at Autojunction option
) @4 u5 j" T- N& D1 genabled was very slow, this has been optimized. q0 i) Z4 Y; B, _5 Y5 L7 j
3779 Improved performance of selection and zooming in Schematic in comparison with 14.3% h; J8 @. W; g
3785 Under certain conditions it was possible to get the PCB Layer Stack Manager graphical3 @% w, r; Z. i. S4 b$ Q
representation out of sync with the tabular layer detail region, this has been resolved.
5 U7 Z+ R0 ~, V" m: b3787 The " rint as a single job" option in Output Job File documents now properly combines the
6 N. l' `. W- a8 @$ Sseparate documents to a single print output7 [* A3 g4 s" ~
3789/ A$ |# k \, C8 K! q& R
PCB re-annotation on a variant design with not-fitted parts could result in the varied parts( I9 `9 y! A0 o G4 ]
becoming out of sync, this no longer occurs. Note: PCB re-annotation on a design that uses
6 p0 G n; H0 z( U1 `" B( \9 Jalternate parts with different footprints is not yet supported.
' \( I5 D$ J5 |/ P3792 STEP models from Inventor 2014 are now loaded without errors0 ^0 f4 s. ^% y% W7 X$ d. j
3800 Variant PCB drawing options have been updated to make it easier to understand how Not
! @8 |# f# @; v9 U$ n! Q8 [0 {Fitted components are displayed.3 U# G3 | U' U. P; V5 C
3809 It is now possible to specify different values for solder mask expansions for top and bottom( C/ P1 [" o# f1 M8 Q
layers5 e( [9 _7 j w' D
3834 Empty surface constructs are now suppressed in ODB++ fabrication output.9 _9 }% ~; X. d6 Z& X
3835 The IPC footprint wizard now correctly supports defining PLCC packages with different D and E+ N3 ~+ s. c" k; B% f r3 Z; R
pin counts, allowing packages with any even number of pins to be created.% t. ^$ ] I' g+ I+ i9 i7 P! E
3836 Dragging multiple schematic wire ends could occasionally result in one wire being shorter
" h; U; V. [+ S# k0 X- Qthan the rest, this no longer occurs.6 ?$ Z# B1 _# k6 z5 A0 l1 @
3841 Reset All command added to the Variant Manager, use this to restore all parameters to& z) R( U, d/ ` k7 Z
alternate or base component values.4 o# S6 C) @$ Q/ |8 w% c" }8 U
3844 The issue resulting in "I/O error 103" error message when some of the project files are
& c: H M) L3 f5 B" q7 ~read-only has been resolved% ]% y" `' h( w6 q0 A! g& N
3845 The speed of updating from libraries or a database has been improved for designs that4 A- Q" N: }7 O1 S
include variants using alternate parts.- Z- R" H+ ^7 z; C% z3 [
3849 In certain circumstances a component would still be shown as varied after resetting8 v& k0 q$ {* e8 i7 L# K: g. E
parameter variations, this has been resolved.
+ T# I: h8 k7 p0 L9 w3857 Polygon management was improved in comparison with 14.3 (restored shelving, modified) y* y% Y: a4 g+ @6 m0 q
concept). W( f; J8 o+ O9 c0 r+ K
3875 The Vaults panel right-click menus now display correctly when Display scaling is being used.
' |; h! R$ ^8 n" s% z6 E, O# `3876 Elements of the Vaults panel were being compressed when Display scaling is being used, this8 g: [6 E* T- e b4 N
no longer occurs.: C* E4 G2 d* A/ ~
3888 Crash reports can now be send from behind a proxy, U k0 K' R2 Q) L0 L9 |/ y0 q' v: q
3889 Simulation Waveform viewer print preview issue has been fixed.* _5 ^4 _- L0 b7 b* K
3900 Class generation settings are now stored for device sheets (BC:3840): _$ ^- B4 t* c. Y0 h# x
3903 The time to open the PCB Classes dialog has been substantially reduced, particularly on
+ o0 k8 x9 {/ |5 v: ~designs with a large number of classes.2 T+ ]# G6 B! |5 q& k
3972 ODB++ output did not generate drill data for drill holes included in a panel, when none of the
2 t/ @2 J" e7 _3 E. Z1 yembedded boards had drill holes, this has been resolved.: J9 U# \& V( ?7 V8 X
3984 Drawing of Schematic Blanket directives has been further optimized to get them to draw2 d9 k" a1 V$ ~4 f4 g# T
quickly and also correctly display the fill color.' V6 z( \ _6 c8 _7 m
4005 Variant designs that include alternate parts with different footprints can now be re-annotated
q# t' R9 s1 I; e5 o/ Z4 N0 v/ vin the PCB editor.
* v N) R# X2 T' F% k& ?4016 PCB DRC now supports stacked alternate parts in a variant-based design. K. ]# L% I& |. X
4049 Signal length column was added to Nets panel (this length is being calculated using more o+ s1 V' `. `3 ]) G7 }. p5 d
precise xSignal engine)* p4 [# M8 D$ F/ ` n+ m) R+ ]
4062 All extensions within a group can now be installed in a single action.
, Y' o4 ^5 o" ^4069 Some PCB dialogs were ignoring the board units and always displaying in mils, this no longer
, W; g( M0 T% R, ~occurs.
4 m; A5 z' U) n/ M6 }4076 Modified Polygon rule support check for shelved polygons+ _7 i+ Z7 `2 z r6 b
4083 During import of a P-CAD PCB file the layer types are now correctly detected and assigned for
' c8 U9 W8 j y. }# g( ^0 Wall possible layer configurations.2 f$ C4 J( S- [6 C
4092 The DRC Violations Display page of the Preferences dialog now displays the complete list of
) Y' T" f+ s$ \Display Style entries when Windows display scaling is being used.5 c2 g/ U5 m; a3 P2 f9 e
4098 An AV could occur while placing a pin in a schematic library and pressing Esc to quit the3 Z6 l5 O' D$ [) Z% X" @
command, this no longer happens.
; t& M3 A! H/ d& h4111 With a specific combination of preferences, placing a component from the schematic libraries
9 @: J. z8 ?1 d6 Q! Bpanel could cause Altium Designer to crash, this no longer occurs.
8 k6 t" D1 f: k" Q$ |( D( g& K4121 After configuring components for pin swapping, it is no longer necessary for the designer to
. d8 l2 Z7 P3 _% Rmanually recompile the design to make those swap configurations available.
2 W) ]6 h d! V; F8 ?" [4133 Changes made in the FPGA Signal Manager are now correctly added to the constraint file.' L. L# v* P/ G' U1 ]
4135 Silk to Solder Mask design rule now correctly detects both silk to solder mask or silk to copper
$ |0 v* d2 I7 |, y8 A% H& y# s/ X3 Jrule check configurations.: j6 d3 `, L8 f1 u% N0 M. S
4215 When a polygon is shelved, connections created by the polygon are maintained internally so
1 e' p$ T" l; o" J% Y4 ~: i4 j* Gthe connection lines will not be displayed.
( l8 `( l( P: k% P4351 NIOS II CPU does not generates with Altera Quartus version 13.0 or later& y0 U. u7 N3 Y: e' O9 _& c& o: c
Source URL: http://techdocs.altium.com/display/ADOH/Release+Notes+for+Altium+Designer+Version+15.0# h8 X/ t! _3 ?+ w: A- \
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发表于 2014-11-21 18:54
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